US 2019/0097055 A1 · BEADED FIN TRANSISTOR

Abstract

Techniques are disclosed for forming a beaded fin transistor. As will be apparent in light of this disclosure, a transistor including a beaded fin configuration may be formed by starting with a multilayer finned structure, and then selectively etching one or more of the layers to form at least one necked (or relatively narrower) portion, thereby forming a beaded fin structure. The beaded fin transistor configuration has improved gate control over a finned transistor configuration having the same top down area or footprint, because the necked/narrower portions increase gate surface area as compared to a non-necked finned structure, such as finned structures used in finFET devices. Further, because the beaded fin structure remains intact (e.g., as compared to a gate-all-around (GAA) transistor configuration where nanowires are separated from each other), the parasitic capacitance problems caused by GAA transistor configurations are mitigated or eliminated.

Claims22

Dependent claims

An integrated circuit including at least one transistor, the integrated circuit comprising:

a gate structure including a gate dielectric and a gate electrode;
and
a fin below the gate structure, the fin also between portions of the gate structure, the fin including
a first layer including a first semiconductor material, the first layer having a first minimum width between the portions of the gate structure, and
a second layer in contact with the first layer, the second layer including a second semiconductor material compositionally different from the first semiconductor material, the second layer having a second minimum width between the portions of the gate structure, the first minimum width less than the second minimum width.

2 more elements

Dependencies are inferred from the claim text.

Beaded fin transistor

Life of this patent

Beaded fin transistor

Life of this patent

Abstract

Claims22