Reducing series resistance between source and/or drain regions and a channel region
AssigneeInternational Business Machines Corporation
InventorsMona A. Ebrish, Oleg Gluschenkov
Life of this patent
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Abstract
A method for reducing series resistance for transistors includes forming a conductive gate over and insulated from a semiconductor substrate, forming source and/or drain extension regions within the substrate and adjacent to respective source and/or drain regions, and forming source and/or drain regions within the substrate. The source and/or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions.
Claims11
A method for reducing lateral series resistance for transistors, the method comprising:
- forming a conductive gate over and insulated from a semiconductor substrate;
- forming source and/or drain extension regions within the substrate;
- and
- forming source and/or drain regions within the substrate and directly underneath and contacting respective source and/or drain extensions regions;
- wherein the source and/or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions.
A method for reducing lateral series resistance for transistors, the method comprising:
- forming a conductive gate over and insulated from a semiconductor substrate;
- forming source and/or drain extension regions within the substrate;
- formed spacers adjacent the conductive gate such that the source and/or drain extension regions directly contact the spacers;
- and
- forming source and/or drain regions within the substrate and directly underneath and contacting respective source and/or drain extensions regions;
- wherein the source and/or drain extension regions are formed from silicon germanium (SiGe) alloyed with tin (Sn) and gallium (Ga), the Sn configured to increase a lattice structure of the SiGe;
- and
- wherein the Sn and Ga are introduced in excess of their chemical solubility.
Dependencies are inferred from the claim text.