Reducing series resistance between source and/or drain regions and a channel region
AssigneeInternational Business Machines Corporation
InventorsMona A. Ebrish, Oleg Gluschenkov
Life of this patent
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Abstract
A method for reducing series resistance for transistors includes forming a conductive gate over and insulated from a semiconductor substrate, forming source and/or drain extension regions within the substrate and adjacent to respective source and/or drain regions, and forming source and/or drain regions within the substrate. The source and/or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions.
Claims10
A structure for reducing lateral series resistance for transistors, the structure comprising:
- a conductive gate formed over and insulated from a semiconductor substrate;
- a sub-fin region disposed in direct contact with the semiconductor substrate;
- source and/or drain extension regions formed in direct contact with the sub-fin region;
- and
- source and/or drain regions disposed in direct contact with the source and/or drain extension regions such that the source and/or drain extension regions are located directly between the sub-fin region and the source and/or drain regions;
- wherein the source and/or drain extension regions are formed from a material alloyed with a first element and a second element, the first element configured to increase a lattice spacing of the material forming the source and/or drain extension regions, and the second element configured to increase electrical conductivity of the source and/or drain extension regions.
10-20. (canceled)
Dependencies are inferred from the claim text.