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US 2019/0097033 A1Published application
High power device
AssigneesKabushiki Kaisha Toshiba, Toshiba Infrastructure Systems & Solutions Corporation
InventorKenichi Sugita
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Abstract
A high power device including with a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer, and a third nitride semiconductor layer containing an Al element formed on the second nitride semiconductor layer. The second nitride semiconductor layer is a multiple quantum well layer in which a nitride semiconductor layer containing an In element and a nitride semiconductor layer not containing an In element are alternately stacked.
Claims11
1:
- A high power device comprising:
- a first nitride semiconductor layer;
- a second nitride semiconductor layer formed on the first nitride semiconductor layer;
- and
- a third nitride semiconductor layer containing an Al element formed on the second nitride semiconductor layer;
- wherein the second nitride semiconductor layer is a multiple quantum well layer in which a nitride semiconductor layer containing an In element and a nitride semiconductor layer not containing an In element are alternately stacked.
3 more elements
2:
- The high power device according to claim 1, wherein:
- the multiple quantum well layer is configured such that an InxGa1-xN layer (1≥x>0) and a GaN layer are alternately stacked,
- a film thickness of the InxGa1-xN layer is not more than 10 nm, and
- a film thickness of the GaN layer is not more than 20 nm.
1 more element
3:
- The high power device according to claim 2, wherein:
- a number of pairs of the InxGa1-xN layer and the GaN layer in the multiple quantum layer is not more than 100.
4:
- The high power device according to claim 1, wherein:
- the third nitride semiconductor layer is an AlyGa1-yN layer (1≥y>0).
5:
- The high power device according to claim 1, further comprising a substrate and a buffer layer provided on the substrate;
- wherein the first nitride semiconductor layer is formed on the buffer layer, and
- wherein the buffer layer is an InaAlbGa(1-a-b)N layer (1≥a≥0, 1≥b≥0).
6:
- The high power device according to claim 4, further comprising a substrate and a buffer layer provided on the substrate;
- wherein the first nitride semiconductor layer is formed on the buffer layer, and
- wherein the buffer layer is an InaAlbGa(1-a-b)N layer (1≥a≥0, 1≥b≥0).
7:
- The high power device according to claim 5, wherein:
- the substrate is any one of Si, SiC, α-Al2O3, ZnO, GaN, AlN and diamond.
8:
- The high power device according to claim 6, wherein:
- the substrate is any one of Si, SiC, α-Al2O3, ZnO, GaN, AlN and diamond.
9:
- The high power device according to claim 1, wherein:
- the multiple quantum well layer is configured such that an InN layer and a GaN layer are alternately stacked,
- a film thickness of the InN layer is 0.26 nm, and
- a film thickness of the GaN layer is not more than 20 nm.
1 more element
10:
- The high power device according to claim 1, wherein in the multiple quantum well layer:
- the nitride semiconductor layer containing an In element is an indium nitride layer (InN), or an indium aluminum gallium nitride layer (InAlGaN) or an indium aluminum nitride layer (InAlN) which has a value of a lower bandgap than a value of a bandgap of gallium nitride (GaN), and
- the nitride semiconductor layer not containing an In element is a GaN layer.
11:
- The high power device according to claim 1, further comprising:
- a source electrode, a gate electrode and a drain electrode which are provided on the third nitride semiconductor layer;
- the source electrode, the gate electrode and the drain electrode being provided separately to each other;
- and
- the source electrode and the drain electrode being provided so as to sandwich the gate electrode.
2 more elements