Split gate memory device and method of fabricating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai
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Abstract
The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a select gate on a side of a sacrificial spacer that is disposed over an upper surface of a substrate. The select gate has a non-planar top surface. An inter-gate dielectric layer is formed on the select gate and a memory gate is formed on the inter-gate dielectric layer. The inter-gate dielectric layer extends under the memory gate and defines a recess between sidewalls of the memory gate and select gate. The recess is filled with a first dielectric material.
Claims20
A method of forming a memory cell, comprising:
- forming a select gate on a side of a sacrificial spacer disposed over an upper surface of a substrate, the select gate having a non-planar top surface;
- forming an inter-gate dielectric layer on the select gate;
- forming a memory gate on the inter-gate dielectric layer, the inter-gate dielectric layer extending under the memory gate and defining a recess between sidewalls of the memory gate and select gate;
- and
- filling of the recess with a first dielectric material.
A method of forming a memory cell, comprising:
- forming a sacrificial layer over a substrate;
- forming a select gate along a side of the sacrificial layer;
- forming a charge trapping layer over the select gate and the sacrificial layer;
- forming a memory gate over the charge trapping layer, wherein the memory gate is laterally separated from the sacrificial layer by the select gate;
- and
- removing the sacrificial layer after forming the memory gate.
A method of forming a memory cell, comprising:
- forming a dielectric layer over a substrate;
- forming a sacrificial dielectric layer contacting an upper surface of the dielectric layer;
- forming a select gate contacting the upper surface of the dielectric layer and along a side of the sacrificial dielectric layer;
- forming a charge trapping layer on the select gate;
- and
- forming a memory gate on the charge trapping layer.
Dependencies are inferred from the claim text.