Memory cell structure of a three-dimensional memory device

A three-dimensional (3D) memory device, comprising:

• an alternating conductor/dielectric stack disposed on a substrate;
• a plurality of channel holes formed on the substrate penetrating the alternating conductor/dielectric stack;
• a channel structure in each channel hole;
• and
• a plurality of gate line slits disposed on the substrate, wherein
• the plurality of channel holes are perpendicular to the substrate and are arranged in a hexagonal lattice orientation comprising a plurality of hexagons,
• each hexagon comprising three pairs of sides, wherein a first pair is perpendicular to a first direction and parallel to a second direction, and wherein the second direction is perpendicular to the first direction, and
• the plurality of gate line slits extend in the first direction.

A method for forming a three-dimensional (3D) memory device, comprising:

• forming an alternating dielectric stack on a substrate;
• forming a staircase structure in the alternating dielectric stack;
• forming a plurality of channel structures in the alternating dielectric stack, each channel structures extending vertically through the alternating dielectric stack, and the plurality of channel structures being arranged in a hexagonal lattice and each hexagon comprising three pairs of sides, wherein a first pair is perpendicular to a first direction and parallel to a second direction, and, wherein the first direction is perpendicular to the second direction;
• forming a slit, and replacing a portion of the alternating dielectric stack with conductor layers to form an alternating conductor/dielectric stack comprising a plurality of conductor/dielectric layers;
• disposing a conductor in the slit to form a slit structure, wherein the slit structure is parallel to a second and a third pair of sides of each hexagon of the hexagonal lattice, forming a zigzag pattern extending in the first direction;
• and
• forming a plurality of contacts on the substrate.