Memory Cells and Memory Arrays

26:

• A memory cell, comprising:
• two pulldown devices and two pullup devices supported by a base;
• the two pulldown devices being first and second pulldown devices, and the two pullup devices being first and second pullup devices;
• the first pullup device and first pulldown device being together comprised by a first inverter;
• the second pullup device and second pulldown device being together comprised by a second inverter;
• the first and second inverters having first and second inverter outputs, respectively;
• the first and second pullup devices being one atop another;
• the first and second pulldown devices being one atop another;
• a first access transistor gatedly coupling the first inverter output to a first comparative bitline;
• the first access transistor having a first access transistor gate;
• a second access transistor gatedly coupling the second inverter output to a second comparative bitline;
• the second access transistor having a second access transistor gate;
• and
• a wordline coupling the first and second access transistor gates to one another;
• the wordline having a first side and an opposing second side;
• the first and second inverters being adjacent the first side of the wordline, and the first and second comparative bitlines being adjacent the second side of the wordline.

30:

• A memory cell, comprising:
• first and second p-channel transistors;
• the first and second p-channel transistors being one atop another;
• first and second n-channel transistors;
• the first and second n-channel transistors being one atop another;
• the first p-channel transistor and first n-channel transistor being together comprised by a first inverter;
• the second p-channel transistor and second n-channel transistor being together comprised by a second inverter;
• the first and second inverters having first and second inverter outputs, respectively;
• a first access transistor gatedly coupling the first inverter output to a first comparative bitline;
• the first access transistor having a first access transistor gate;
• a second access transistor gatedly coupling the second inverter output to a second comparative bitline;
• the second access transistor having a second access transistor gate;
• the first and second access transistor gates being coupled to one another through a wordline;
• the wordline having a first side and an opposing second side;
• the first and second p-channel transistors and the first and second n-channel transistors, being adjacent the first side of the wordline;
• and
• the first and second comparative bitlines being adjacent the second side of the wordline.

31:

• The memory cell of claim 30, wherein:
• the first and second n-channel transistors are comprised by a first stack;
• the first and second p-channel transistors are comprised by a second stack;
• and
• the second stack is laterally displaced from the first stack and horizontally aligned with the first stack.

32:

• A memory array comprising the memory cell of claim 31 as one memory cell within a plurality of memory cells;
• wherein
• an axis through the first and second comparative bitlines defines a mirror plane;
• and
• another memory cell is on an opposing side of the mirror plane from said one memory cell and is substantially a mirror image of said one memory cell across the mirror plane;
• said other memory cell sharing the first and second comparative bitlines with said one memory cell.

35:

• The memory cell of claim 33, wherein:
• the first p-channel transistor has a first pullup gate surrounding a first channel region;
• the second p-channel transistor has a second pullup gate surrounding a second channel region;
• the first n-channel transistor has a first pulldown gate surrounding a third channel region;
• the second n-channel transistor has a second pulldown gate surrounding a fourth channel region;
• the first, second, third and fourth channel regions are within first, second third and fourth vertically-extending pillars, respectively;
• and
• the second vertically-extending pillar is over the first vertically-extending pillar which is over the third vertically-extending pillar which is over the fourth vertically-extending pillar.

37:

• The memory cell of claim 36, wherein
• a first circuit supply line is vertically between the first and second p-channel transistors and is coupled with source regions of the first and second p-channel transistors;
• a second circuit supply line is vertically between the first and second n-channel transistors and is coupled with source regions of the first and second n-channel transistors;
• the first circuit supply line is coupled with a first reference voltage and the second circuit supply line is coupled with a second reference voltage;
• and
• the first reference voltage is higher than the second reference voltage.

38:

• A memory array comprising the memory cell of claim 30 as one memory cell within a plurality of memory cells;
• wherein
• an axis through the first and second comparative bitlines defines a mirror plane;
• and
• another memory cell is on an opposing side of the mirror plane from said one memory cell and is substantially a mirror image of said one memory cell across the mirror plane;
• said other memory cell sharing the first and second comparative bitlines with said one memory cell.

39:

• An apparatus comprising:
• a memory array having rows and columns:
• the memory array being supported by a silicon-containing base;
• wordlines along the rows;
• comparative bitlines along the columns;
• the comparative bitlines being in pairs along each column;
• each pair of the comparative bitlines including a first comparative bitline and a second comparative bitline;
• a plurality of memory cells;
• each memory cell within the plurality of memory cells being uniquely addressed with one of the wordlines and one pair of the comparative bitlines;
• each memory cell within the plurality of memory cells comprising two p-channel transistors and two n-channel transistors, with the p-channel and n-channel transistors being arranged within a first inverter and a second inverter;
• the first and second inverters having first and second inverter outputs, respectively;
• each memory cell within the plurality of memory cells comprising a first access transistor gatedly coupling the first inverter output with a first comparative bitline of a pair of comparative bitlines uniquely addressing the memory cell, and a second access transistor gatedly coupling the second inverter output with a second comparative bitline of the pair of comparative bitlines uniquely addressing the memory cell;
• the first and second access transistors having gates coupled with a wordline uniquely addressing the memory cell;
• one of the memory cells within the plurality of memory cells being a first memory cell and being uniquely addressed by a first wordline and a first pair of the comparative bitlines;
• the first and second comparative bitlines of said first pair being laterally adjacent to one another and on an opposing side of the first wordline from the p-channel transistors and the n-channel transistors of the first memory cell;
• one of the memory cells within the plurality of memory cells being a second memory cell vertically stacked relative to the first memory cell and sharing the first pair of the comparative bitlines;
• and
• the second memory cell being substantially a mirror image of the first memory cell across a plane extending through the first pair of the comparative bitlines.

40:

• The apparatus of claim 39 comprising a second wordline utilized with the first pair of the comparative bitlines to uniquely address the second memory cell;
• the first and second memory cells being a first set of stacked memory cells;
• one of the memory cells within the plurality of memory cells being a third memory cell, and another memory cell within the plurality of memory cells being a fourth memory cell;
• and the apparatus comprising:
• the third and fourth memory cells being laterally adjacent the first and second memory cells;
• the third and fourth memory cells being vertically stacked one atop another and being a second set of stacked memory cells laterally displaced from the first set of stacked memory cells along the first and second wordlines;
• and
• the third and fourth memory cells being substantially mirror images of one another across a plane extending through a second pair of the comparative bitlines.