Static random access memory structure

A static random access memory (SRAM) structure, comprising:

• a substrate;
• a first inverter comprising a first pull-up transistor (PL1) and a first pull-down transistor (PD1) disposed on the substrate;
• a second inverter comprising a second (PL2) and a second pull-down transistor (PD2) on the substrate, wherein the first inverter and the second inverter are cross-coupled to each other;
• a first pass gate transistor (PG1A) and a second pass gate transistor (PG1B) electrically connected to an output terminal of the first inverter, a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B) electrically connected to an output terminal of the second inverter, wherein a gate of the PG1A and a gate of the PG2A electrically connected to a first word line, a gate of the PG1B and a gate of the PG2B electrically connected to a second word line;
• a plurality of transistors including the PL1, the PL2, the PD1, the PD2, the PG1A, the PG1B, the PG2A and the PG2B, each transistor comprises a gate structure crosses over a diffusion region, wherein the PG1A and the PG1B comprise a first diffusion region, the PG2A and the PG2B comprise a second diffusion region;
• a first local interconnection layer disposed between the PG1A and the PG1B, and disposed on the first diffusion region of the PG1A, the first diffusion region of the PG1B, the diffusion region of the PL1 and the diffusion region of the PD1, wherein the first local interconnection layer is a monolithically formed structure;
• and
• a second local interconnection layer disposed between the PG2A and the PG2B, and disposed on the second diffusion region of the PG2A, the second diffusion region of the PG2B, the diffusion regions of the PL2 and the diffusion region of the PD2, wherein the first local interconnection layer is a monolithically formed structure.