Complimentary Metal-Oxide-Semiconductor (CMOS) with Low Contact Resistivity and Method of Forming Same

An integrated circuit device comprising:

• a semiconductor substrate;
• a gate stack over the semiconductor substrate;
• a source/drain region on a side of the gate stack, wherein a part of the source/drain region extends into the semiconductor substrate;
• a metal contact overlapping the source/drain region;
• and
• a titanium-containing dielectric layer on a sidewall of the metal contact.

An integrated circuit device comprising:

• an n-type metal-oxide-semiconductor (NMOS) device comprising:
• a first source/drain region comprising silicon;
• a first dielectric layer over the first source/drain region;
• a first contact plug over the first source/drain region and in the first dielectric layer;
• a first titanium oxide layer comprising sidewall portions separating the first contact plug from the first dielectric layer, and a bottom portion separating the first source/drain region from the first contact plug;
• and
• a p-type metal-oxide-semiconductor (PMOS) device comprising:
• a second source/drain region comprising silicon germanium;
• a second dielectric layer over the second source/drain region;
• a second contact plug over the second source/drain region and in the second dielectric layer;
• a second titanium oxide layer comprising sidewall portions separating the second contact plug from the second dielectric layer;
• and
• a compound region comprising a compound of titanium and a material selected from silicon, germanium, and combinations thereof, wherein a top surface of the compound region contacts the second contact plug, and a bottom surface of the compound region contacts the second source/drain region.