Semiconductor device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Yuan LU, Sai-Hooi YEONG
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Abstract
In in a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.
Claims20
A semiconductor device, comprising:
- a gate structure disposed over a channel region of a fin structure;
- a source/drain structure disposed at a source/drain region of the fin structure;
- an etch-stop layer covering side faces of the source/drain structure;
- and
- a conductive contact disposed over the source/drain structure, wherein:
- the source/drain structure includes a first epitaxial layer and a second epitaxial layer disposed over the first epitaxial layer, and
- the second epitaxial layer is disposed on an upper portion of the etch-stop layer.
A semiconductor device, comprising:
- a first fin field effect transistor (FinFET) including a first gate structure disposed over a first channel region of a first fin structure, a first source/drain structure disposed at a first source/drain region of the first fin structure, and a first etch-stop layer covering side faces of the first source/drain structure;
- a second FinFET including a second gate structure disposed over a second channel region of a second fin structure, a second source/drain structure disposed at a second source/drain region of the second fin structure, and a second etch-stop layer covering side faces of the second source/drain structure, wherein:
- the first FinFET is first conductivity-type and the second FinFET is second conductive type,
- the first source/drain structure includes a first lower epitaxial layer and a first upper epitaxial layer disposed over the first lower epitaxial layer, and
- the first upper epitaxial layer is disposed on an upper portion of the first etch-stop layer.
A semiconductor device, comprising:
- a gate structure disposed over a channel region of a first fin structure and a channel region of a second fin structure;
- a first epitaxial layer disposed at a source/drain region of the first fin structure;
- a second epitaxial layer disposed at a source/drain region of the second fin structure;
- a third epitaxial layer;
- and
- an etch-stop layer covering side faces of the first and second source/drain epitaxial layers, wherein:
- the third epitaxial layer is disposed on upper portions of the etch-stop layer and on the first and second epitaxial layers.
Dependencies are inferred from the claim text.