US 2019/0096877 A1Published application

Integrated Resistor for Semiconductor Device

AssigneePower Integrations, Inc.

InventorsAlexey Kudymov, Jamal Ramdani

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Abstract

A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.

Claims21

Dependent claims

A heterostructure semiconductor device comprising:

a first active layer;
a second active layer disposed on the first active layer, an electrical charge layer being disposed between the first and second active layers;
a power transistor having a first active area which includes a first portion of the first active layer and a first portion of the second active layer, in operation, a current flowing through a first portion of the electrical charge layer;
a gate array that laterally extends over the first active area of the power transistor, the gate array functioning as a gate of the power transistor;
a gate resistor having a second active area which includes a second portion of the first active layer, a second portion of the second active layer, and a second portion of the electrical charge layer, the second active area being electrically isolated from the first active area;
first and second contacts respectively disposed at first and second lateral ends of the gate resistor, the first and second contacts being electrically connected to the second portion of the second active layer, the second contact also being electrically connected to the gate array;
and
a gate bus electrically connected to the first contact.

5 more elements

A method of fabricating a heterostructure semiconductor device comprising:

forming a first active layer on a substrate;
forming a second active layer on the first active layer, the first active layer and the second active layer having different bandgaps such that an electrical charge layer is formed therebetween;
defining a first active area and a second active area, the first active area including a first portion of the first active layer, a first portion of the second active layer, and a first portion of the electrical charge layer, the second active area including a second portion of the first active layer, a second portion of the second active layer, and a second portion of the electrical charge layer, the second active area being electrically isolated from the first active area, wherein the first active area comprises a power transistor and the second active area comprises an integrated gate resistor of the heterostructure semiconductor device;
forming first and second contacts directly on the second portion of the second active layer, the first and second contacts being laterally separated by a distance, the first and second contacts comprising first and second terminals of the integrated gate resistor, respectively;
and
forming an array of gates that laterally extends over the first active area of the power transistor, the array of gates being electrically connected to the second contact and functioning as a gate of the power transistor.

3 more elements

Dependencies are inferred from the claim text.