Semiconductor Device Layout

A semiconductor device comprising:

• a double-fin active region including:
• a first pair of fins,
• a second pair of fins parallel to the first pair of fins,
• a first n-type field effect transistor (FET) including a first gate structure disposed over the first pair of fins and first source/drain (S/D) contacts on either side of the first gate structure, each of the first S/D contacts being disposed over the first pair of fins,
• a first p-type FET, including the first gate structure disposed over the second pair of fins and second source/drain (S/D) contacts on either side of the first gate structure, each of the second S/D contacts being disposed over the second pair of fins;
• a mono-fin active region abutting the double-fin active region, the mono-fin active region including:
• a first fin,
• a second fin different from the first fin,
• a second n-type FET including a second gate structure disposed over the first fin and third S/D contacts on either side of the second gate structure, each of the third S/D contacts being disposed over the first fin,
• a second p-type FET including the second gate structure disposed over the second fin and fourth S/D contacts on either side of the second gate structure, each of the fourth S/D contacts being disposed over the second fin;
• and
• an isolation feature between the double-fin active region and the mono-fin active region, the isolation feature being parallel to the first and second gate structures.

A semiconductor device comprising:

• a first region including:
• a first pair of fins over a P-type well in a semiconductor substrate,
• a second pair of fins parallel to the first pair of fins, the second pair of fins being over an N-type well in the semiconductor substrate,
• a first field effect transistor (FET) including a first gate structure disposed over the first pair of fins and first source/drain (S/D) contacts on either side of the first gate structure, each of the first S/D contacts being disposed over the first pair of fins,
• a second FET, including the first gate structure disposed over the second pair of fins and second source/drain (S/D) contacts on either side of the first gate structure, each of the second S/D contacts being disposed over the second pair of fins;
• a second region abutting the first region, the second region including:
• a first fin over the P-type well in the semiconductor substrate,
• a second fin different from the first fin, the second fin being over the P-type well in the semiconductor substrate,
• a third FET including a second gate structure disposed over the first fin and third S/D contacts on either side of the second gate structure, each of the third S/D contacts being disposed over the first fin,
• a fourth FET including the second gate structure disposed over the second fin and fourth S/D contacts on either side of the second gate structure, each of the fourth S/D contacts being disposed over the second fin;
• and
• an isolation feature between the first region and the second region, the isolation feature being parallel to the first and second gate structures.