US 2019/0096866 A1Published application

Semiconductor package and manufacturing method thereof

AssigneePowertech Technology Inc.

InventorsChing-Ming Hsu, Wen-Hsiung Chang, Po-Wei Yeh, Yun-Hsin Yeh

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Abstract

A semiconductor package including a first semiconductor chip, a plurality of first conductors, a first conductive pattern electrically connected to the first conductors, a second semiconductor chip disposed on the first semiconductor chip, and an encapsulant on the first conductive pattern and laterally encapsulating the second semiconductor chip. The first semiconductor chip electrically connected to the first conductors includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending form the first back surface towards the first active surface. The second semiconductor chip including a second active surface facing towards the first back surface electrically connects the first semiconductor chip through the first conductors in the through holes and the first conductive pattern on the first back surface. A manufacturing method of a semiconductor package is also provided.

Claims20

Dependent claims

A semiconductor package, comprising:

a plurality of first semiconductor chips, each of the first semiconductor chips comprising a first active surface, a sensing area on the first active surface, a first back surface opposite to the first active surface and a plurality of through holes extending form the first back surface towards the first active surface, wherein one of the first semiconductor chips collects wavelengths of light different from wavelengths of light collected by another of the first semiconductor chips, and spectral responsivities of the first semiconductor chips are complementary to one another;
a plurality of first conductors disposed in the through holes of the first semiconductor chips and electrically connected to the first semiconductor chips;
a first conductive pattern disposed on the first back surfaces of the first semiconductor chips and electrically connected to the first conductors;
a second semiconductor chip disposed on the first conductive pattern and comprising a second active surface facing towards the first back surfaces of the first semiconductor chips, wherein the second semiconductor chip is electrically connected to the first semiconductor chips through the first conductive pattern;
and
an encapsulant disposed on the first conductive pattern and laterally encapsulating the second semiconductor chip.

3 more elements

A manufacturing method of a semiconductor package, comprising:

providing a plurality of first semiconductor chips, wherein each of the first semiconductor chips comprises a first active surface, a sensing area on the first active surface, a first back surface opposite to the first active surface and a plurality of through holes extending from the first back surface towards the first active surface, and one of the first semiconductor chips collects wavelengths of light different from wavelengths of light collected by another of the first semiconductor chips, and spectral responsivities of the first semiconductor chips are complementary to one another;
forming a plurality of first conductors in the through holes of the first semiconductor chips;
forming a first conductive pattern on the first back surface of each of the first semiconductor chips to electrically connect the first conductors;
disposing a second semiconductor chip on the first conductive pattern, wherein the second semiconductor chip comprises a second active surface facing towards the first back surface of each of the first semiconductor chips, and the second semiconductor chip is electrically connected to the first semiconductor chips;
and
forming an encapsulant on the first conductive pattern to laterally encapsulate the second semiconductor chip.

3 more elements

Dependencies are inferred from the claim text.