# US 2019/0096862 A1 · Semiconductor Packages and Methods of Forming Same

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- Number: US 2019/0096862 A1
- Document ID: US20190096862A1
- Status: Published application
- Kind: A1
- Application number: 16/206,281
- Filed: 2018-11-30
- Published: 2019-03-28
- Earliest claimed: 2017-03-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hua Yu; Der-Chyang Yeh; Han-Ping Pu
- Web page: https://patentgrep.com/patent/US20190096862A1

## CPC

- H10W 90/00: Package configurations
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/69: Insulating materials thereof
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01236: {in solid form, e.g. by using a powder or by laminating a foil}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01257: {by reflowing}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/01955: {by using masks}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07255: {changes in materials}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/2528: {Intermetallic compounds}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/30: Die-attach connectors
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/90: Bond pads, in general
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/314: {characterized by direct bonding of pads or other interconnections}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An embodiment is a package including a first package structure. The first package structure includes a first integrated circuit die having an active side and a back-side, the active side comprising die connectors, a first electrical connector adjacent the first integrated circuit die, an encapsulant laterally encapsulating the first integrated circuit die and the first electrical connector, a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the first electrical connector, and thermal elements on the back-side of the first integrated circuit die. The package further includes a second package structure bonded to the first electrical connector and the thermal elements with a first set of conductive connectors.

## Claims

### Claim 1

A package comprising:
a first package structure comprising:
a first integrated circuit die having an active side and a back-side, the active side comprising die connectors;
a first through via adjacent the first integrated circuit die;
an encapsulant laterally encapsulating the first integrated circuit die and the first through via;
a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the first through via; and
thermal elements on the back-side of the first integrated circuit die; and
a second package structure bonded to the first through via and the thermal elements with a first set of conductive connectors.

### Claim 2 (depends on 1)

The package of claim 1, wherein the thermal elements are electrically isolated from integrated circuits within the first integrated circuit die.

### Claim 3 (depends on 1)

The package of claim 1, wherein the back-side of the first integrated circuit die is recessed from a surface of the encapsulant, the thermal elements being within the recess.

### Claim 4 (depends on 1)

The package of claim 1, wherein the thermal elements have sidewalls that are perpendicular to the back-side of the first integrated circuit die.

### Claim 5 (depends on 1)

The package of claim 1, wherein the thermal elements have sidewalls that taper from top surfaces to bottom surfaces of the thermal elements.

### Claim 6 (depends on 1)

The package of claim 1, wherein the thermal elements have sidewalls that widen from top surfaces to bottom surfaces of the thermal elements.

### Claim 7 (depends on 1)

The package of claim 1, wherein the thermal elements comprise a conductive paste and metallization patterns.

### Claim 8 (depends on 1)

The package of claim 1 further comprising:
an underfill surrounding the first set of conductive connectors, the underfill being between the first package structure and the second package structure.

### Claim 9 (depends on 8)

The package of claim 8, wherein the underfill contacts the thermal elements.

### Claim 10 (depends on 1)

The package of claim 1, wherein a central portion between the first package structure and the second package structure is free from conductive connectors.

### Claim 11 (depends on 1)

The package of claim 1 further comprising:
vias within the back-side of the first integrated circuit die, the thermal elements being thermally connected to the vias.

### Claim 12 (depends on 1)

The package of claim 1, wherein the first package structure further comprises:
a second redistribution structure over the electrically connected to the first through via, the second redistribution structure being between the first integrated circuit die and the second package structure.

### Claim 13 (depends on 1)

The package of claim 1 further comprising:
a dummy die on the back-side of the first integrated circuit die, the thermal elements being on the dummy die.

### Claim 14

A package comprising:
a first package structure comprising:
a dummy die having a front-side and a back-side;
a first integrated circuit die having a front-side and a back-side, the front-side comprising die connectors;
a first attaching layer between and contacting the back-side of the first integrated circuit die and front-side of the dummy die;
a first electrical connector adjacent the first integrated circuit die, the first attaching layer, and the dummy die;
an encapsulant laterally encapsulating the first integrated circuit die, the dummy die, the first attaching layer, and the first electrical connector;
a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the first electrical connector; and
thermal elements on the back-side of the dummy die; and
a second package structure bonded to the first electrical connector and the thermal elements with a first set of conductive connectors.

### Claim 15 (depends on 14)

The package of claim 14, wherein the first attaching layer is a conductive layer comprising a metal.

### Claim 16 (depends on 14)

The package of claim 14, wherein the dummy die is made of metal.

### Claim 17 (depends on 14)

The package of claim 14, wherein the back-side of the dummy die is recessed from a surface of the encapsulant, the thermal elements being within the recess.

### Claim 18

A structure comprising:
a first package structure comprising:
a first redistribution structure comprising metallization patterns and dielectric layers;
a first die over and electrically connected to the first redistribution structure, an active side of the first die comprising die connectors facing the first redistribution structure;
a first through via adjacent the first die, the first through via electrically connected to the first redistribution structure;
an encapsulant laterally encapsulating the first die and the through via;
an attaching layer over a back-side of the first die, the back-side of the first die being opposite the active side, the attaching layer contacting the encapsulant; and
a second redistribution structure over the attaching layer and the first through via, the second redistribution structure comprising metallization patterns and a dielectric layer, the second redistribution structure being electrically connected to the first through via; and
a second package structure bonded to the metallization patterns of the second redistribution structure with a first set of conductive connectors.

### Claim 19 (depends on 18)

The structure of claim 18, wherein the attaching layer is a conductive paste.

### Claim 20 (depends on 18)

The structure of claim 18, wherein the first die further comprises thermal dissipation paths, and wherein the attaching layer is connected to the thermal dissipation paths of the first die.