Microelectronic package for wafer-level chip scale packaging with fan-out
AssigneeInvensas Corporation
InventorsRajesh Katkar, Ashok S. Prabhu
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Abstract
Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.
Claims20
A microelectronic package for wafer-level chip scale packaging with fan-out, comprising:
- a substrate having an upper surface and a lower surface opposite the upper surface;
- a microelectronic device coupled to the upper surface with the microelectronic device in a face-up orientation;
- wire bond wires coupled to and extending away from the upper surface;
- posts of the microelectronic device extending away from a face of the microelectronic device facing away from the substrate;
- and
- conductive pads formed in the substrate associated with the wire bond wires for electrical conductivity.
Dependencies are inferred from the claim text.