Hybrid 3d/2.5d interposer
AssigneeInvensas Corporation
InventorsCharles G. Woychik, Cyprian Emeka Uzoh, Sangil Lee, Liang Wang, Guilian Gao
Life of this patent
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Abstract
Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.
Claims22
A method, comprising:
- providing a carrier having a first surface and a second surface;
- forming a first plurality of pockets on the first surface of the carrier according to a first predetermined pattern to match a pitch of terminals of a first microelectronic component, the first plurality of pockets being etched to different depths, one or more pockets of the first plurality of pockets being exposed through to the second surface of the carrier;
- and
- forming a second plurality of pockets on the first surface of the carrier according to a second predetermined pattern to match a pitch of terminals of a second microelectronic component, the second plurality of pockets being etched to different depths, one or more pockets of the second plurality of pockets being exposed through to the second surface of the carrier.
A microelectronic package arrangement, comprising:
- an interposer, including a carrier having a first surface and a second surface;
- a first plurality of pockets disposed at first predetermined locations on the first surface of the carrier having a spacing that matches a pitch of terminals of a first microelectronic component to be inserted into the first plurality of pockets, the first plurality of pockets being etched to different depths, one or more pockets of the first plurality of pockets being exposed through to the second surface of the carrier;
- a second plurality of pockets disposed at second predetermined locations on the first surface of the carrier having a spacing that matches a pitch of terminals of a second microelectronic component to be inserted into the second plurality of pockets, the second plurality of pockets being etched to different depths, one or more pockets of the second plurality of pockets being exposed through to the second surface of the carrier;
- and
- a conductive material disposed at least within the one or more pockets of the first plurality of pockets and the one or more pockets of the second plurality of pockets exposed through to the second surface of the carrier.
Dependencies are inferred from the claim text.