US 2019/0096811 A1Published application

Integrated circuit and method of manufacturing same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsPochun WANG, Ting-Wei CHIANG, Chin-Ming LAI, Hui-Zhong ZHUANG, Jung-Chan YANG, Ru-Gun LIU, Yai-Chi CHOU, Yi-Hsiung LIN, Yu-Xuan HUANG, Yu-Jung CHANG, Guo-Huei WU, Shih-Ming CHANG

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Abstract

An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

Claims20

Dependent claims

An integrated circuit comprising:

a set of active regions in a substrate, the set of active regions extending in a first direction, being located on a first level, and being separated from one another in a second direction different from the first direction;
a first set of conductive structures extending in at least the first direction or the second direction, being located on the first level, and being between the set of active regions;
a shallow trench isolation (STI) region extending in at least the first direction or the second direction, being located on at least the first level, and being between the set of active regions and the first set of conductive structures;
a set of gates extending in the second direction, overlapping at least the first set of conductive structures and being located on a second level different from the first level, each of the gates of the set of gates being separated from an adjacent gate of the set of gates in the first direction by a first pitch;
and
a set of contacts extending in the second direction, overlapping the first set of conductive structures, and being located on the second level, each of the contacts of the set of contacts being separated from an adjacent contact of the set of contacts in the first direction.

3 more elements

A method of forming an integrated circuit, the method comprising:

generating, by a processor, a layout design of the integrated circuit, wherein the generating of the layout design comprises:
generating a set of active region layout patterns extending in a first direction, being located on a first layout level, and being separated from one another in a second direction different from the first direction, the set of active region layout patterns corresponding to fabricating a set of active regions within a substrate of the integrated circuit;
generating a first set of conductive feature layout patterns extending in at least the first direction or the second direction, being located on the first layout level, and being between the set of active region layout patterns, the first set of conductive feature layout patterns corresponding to fabricating a first set of conductive structures of the integrated circuit within the substrate;
generating a set of gate layout patterns extending in the second direction, overlapping at least the first set of conductive feature layout patterns and being located on a second layout level different from the first layout level, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in the first direction by a first pitch, the set of gate layout patterns corresponding to fabricating a set of gates of the integrated circuit;
generating a set of metal over diffusion layout patterns corresponding to fabricating a set of contacts of the integrated circuit, the set of metal over diffusion layout patterns extending in the second direction, overlapping the first set of conductive feature layout patterns, and being located on the second layout level, each of the layout patterns of the set of metal over diffusion patterns being separated from an adjacent layout pattern of the set of metal over diffusion layout patterns in the first direction;
and
generating a first set of via layout patterns corresponding to fabricating a first set of vias, the first set of vias coupling the first set of conductive structures to the set of contacts, the first set of via layout patterns being between the first set of conductive feature layout patterns and the set of metal over diffusion layout patterns, and a layout pattern of the first set of via layout patterns being located where a layout pattern of the set of metal over diffusion layout patterns overlaps the layout pattern of the first set of conductive feature layout patterns;
and
manufacturing the integrated circuit based on the layout design.

6 more elements

A method of forming an integrated circuit, the method comprising:

generating, by a processor, a layout design of the integrated circuit, wherein the generating of the layout design comprises:
placing a set of active region layout patterns on a first layout level, the set of active region layout patterns extending in a first direction, and being separated from one another in a second direction different from the first direction, the set of active region layout patterns corresponding to fabricating a set of active regions within a substrate of the integrated circuit;
placing a first set of conductive feature layout patterns on the first layout level, the first set of conductive feature layout patterns extending in at least the first direction or the second direction, and being between the set of active region layout patterns, the first set of conductive feature layout patterns corresponding to fabricating a first set of conductive structures within the substrate of the integrated circuit;
placing a set of metal over diffusion layout patterns on a second layout level different from the first layout level, the set of metal over diffusion layout patterns corresponding to fabricating a set of contacts of the integrated circuit, the set of metal contacts being electrically coupled to the active regions of the integrated circuit, the set of metal over diffusion layout patterns extending in the second direction, and overlapping the first set of conductive feature layout patterns, each of the layout patterns of the set of metal diffusion patterns being separated from an adjacent layout pattern of the set of metal over diffusion layout patterns in the first direction;
and
placing a first set of via layout patterns between the first set of conductive feature layout patterns and the set of metal over diffusion layout patterns, the first set of via layout patterns corresponding to fabricating a first set of vias, the first set of vias coupling the first set of conductive structures to the set of contacts, and a layout pattern of the first set of via layout patterns being located where a layout pattern of the set of metal over diffusion layout patterns overlaps the layout pattern of the first set of conductive feature layout patterns;
and
manufacturing the integrated circuit based on the layout design, the integrated circuit comprising a transmission gate.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/135,684Filed 19 Sep 2018
Priority: 28 Sep 2017
Published: 28 Mar 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
G06F 30/39
Circuit design: circuit design at the physical level
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
H10D 84/0193
The components including complementary IGFETs, e.g. CMOS devices: the components including FinFETs