Word line contact structure for three-dimensional memory devices and fabrication methods thereof

A semiconductor structure, comprising:

• a staircase structure comprising a plurality of steps, wherein each step comprises a conductive layer disposed over a dielectric layer;
• an etch-stop layer disposed over a portion of the conductive layer of the each step;
• an insulating layer disposed on the etch-stop layer;
• and
• a plurality of conductive structures formed in the insulating layer and extending through the etch-stop layer, wherein each conductive structure directly contacts the corresponding conductive layer of each step.

A method for forming a semiconductor structure, comprising:

• forming a staircase structure having a plurality of steps, wherein the forming of each step of the plurality of steps comprises disposing a sacrificial layer over a dielectric layer;
• disposing an etch-stop layer on each step of the plurality of steps;
• disposing an insulating layer on the etch-stop layer;
• replacing the sacrificial layer of each step with a conductive layer;
• forming a plurality of openings in the insulating layer exposing portions of the etch-stop layer;
• etching the exposed portions of the etch-stop layer in the plurality of openings and exposing at least a portion of the conductive layer of each step;
• and
• forming a plurality of conductive structures in each of the plurality of openings.