Standard cells having via rail and deep via structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Cheng Lin, Cheng-Chi Chuang, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Wayne Lai
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Abstract
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.
Claims20
A semiconductor structure comprising:
- a plurality of gate structures;
- a plurality of vias formed in a first dielectric layer, wherein each via of the plurality of vias is formed on each gate structure of the plurality of gate structures;
- a conductive rail structure formed in the first dielectric layer and over at least one via of the plurality of vias, wherein the conductive rail structure is electrically connected to the at least one via of the plurality of vias;
- a second dielectric layer formed over the first dielectric layer and the conductive rail structure;
- a deep via formed at least in the second dielectric layer and over the conductive rail structure, wherein the deep via is electrically connected to the conductive rail structure;
- and
- a first plurality of metal lines formed over and electrically connected to the deep via.
A standard cell structure comprising:
- a plurality of source/drain (S/D) contact structures;
- a via rail structure formed in a first dielectric layer and over two or more S/D contact structures of the plurality of S/D contact structures;
- a local interconnect line in parallel with the via rail structure, wherein the local interconnect line is in a different interconnect level than the via rail structure;
- a second dielectric layer formed over the first dielectric layer and the via rail structure;
- a deep via formed at least in the second dielectric layer and over the via rail structure, wherein the deep via is electrically connected to the via rail structure;
- and
- one or more conductive structures formed over and electrically connected to the deep via.
A method of forming a semiconductor structure comprising:
- forming a plurality of source/drain (S/D) contact structures;
- etching a first trench;
- depositing a first conductive material into the first trench to form a via rail structure over two or more S/D contact structures of the plurality of S/D contact structures, wherein the via rail structure is in a different interconnect level than a local interconnect line of the semiconductor structure;
- etching a second trench;
- depositing a second conductive material into the second trench to form a deep via over and electrically connected to the via rail structure;
- etching a third trench;
- and
- depositing a third conductive material into the third trench to form one or more conductive structures over and electrically connected to the deep via.
Dependencies are inferred from the claim text.