Novel mim structure

A semiconductor device comprising:

• first and second conductive features on a semiconductor substrate;
• first and second metallization layers configured on the semiconductor substrate above the first and second conductive features, wherein the first and second metallization layers each comprises a respective metallization structure formed in a respective dielectric layer;
• first and second via structures in respective dielectric layers, wherein the first via structure extends from the first conductive feature to the first metallization layer and wherein the second via structure extends from the first metallization layer to the second metallization layer so as to electrically couple the second metallization structure to the first conductive feature through the first metallization structure;
• a conductive etch stop structure at the bottom of the second via structure and on at least part of the first metallization structure of the first metallization layer to electrically couple the first metallization structure and the second via structure;
• and
• a capacitor embedded and oriented transversely in a plurality of dielectric layers.

A semiconductor device comprising:

• a plurality of metallization structures electrically coupled through a plurality of via structures in a plurality of dielectric layers;
• a plurality of conductive etch stop structures on the plurality of metallization structures;
• and
• a plurality of capacitors embedded and oriented transversely in the plurality of dielectric layers, wherein each of the capacitors comprises a capacitor dielectric layer sandwiched between first and second metal electrodes.