Dual Damascene Process for Forming Vias and Interconnects in an Integrated Circuit Structure

A method of forming conductive structures in a semiconductor device, the method comprising:

• forming a mask over a non-conductive structure, the mask including a first mask opening and a second mask opening, the first mask opening having a greater width than the second mask opening;
• etching through the first and second mask openings into the non-conductive structure to define:
• a via trench having a via trench opening width defined by the first mask opening;
• and
• an interconnect trench having an interconnect trench width defined by the second mask opening and smaller than the via trench width;
• depositing a fill layer extending into both the via trench and the interconnect trench such that:
• the fill layer extending into the via trench fills only a portion of the via trench width to thereby define an open via trench cavity;
• and
• the fill layer extending into the interconnect trench fills the full interconnect trench width;
• etching through the via trench cavity to form a via opening extending downwardly from the via trench;
• removing the fill layer from the via trench and the interconnect trench;
• filling the interconnect trench, the via trench, and the via opening with a conductive material to form (a) a trench interconnect in the interconnect trench, (b) a via interconnect in the via trench, and (c) a via in the via opening, wherein the via extends downwardly from the via interconnect.