Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress

A method of preparing a multilayer structure, the method comprising:

• forming a semiconductor oxide layer, a semiconductor nitride layer, or a semiconductor oxynitride layer in interfacial contact with a front surface of a single crystal semiconductor handle substrate, the single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm;
• annealing the single crystal semiconductor handle substrate comprising the semiconductor oxide layer, the semiconductor nitride layer, or the semiconductor oxynitride layer in interfacial contact with the front surface thereof in an ambient atmosphere comprising a gas selected from the group consisting of hydrogen, hydrogen chloride, chlorine, and any combination thereof, wherein the anneal of the single crystal semiconductor handle substrate comprising the semiconductor oxide layer, the semiconductor nitride layer, or the semiconductor oxynitride layer forms a textured semiconductor oxide layer comprising holes having sizes between about 5 nanometers and about 1000 nanometers, a textured semiconductor nitride layer comprising holes having sizes between about 5 nanometers and about 1000 nanometers, or a textured semiconductor oxynitride layer comprising holes having sizes between about 5 nanometers and about 1000 nanometers;
• exposing the single crystal semiconductor handle substrate comprising the semiconductor oxide layer, the semiconductor nitride layer, or the semiconductor oxynitride layer in interfacial contact with the front surface thereof to an ambient atmosphere comprising a silicon precursor at a temperature of at least about 850° C. to thereby deposit a polycrystalline silicon layer on the textured semiconductor oxide layer, the textured semiconductor nitride layer, or the textured semiconductor oxynitride layer;
• and
• bonding a dielectric layer on a front surface of a single crystal semiconductor donor substrate to the polycrystalline silicon layer of the single crystal semiconductor handle substrate to thereby form a bonded structure, wherein the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, and a central plane between the front and back surfaces of the semiconductor donor substrate.

A multilayer structure comprising:

• a single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm;
• a textured semiconductor oxide layer, a textured semiconductor nitride layer, or a textured semiconductor oxynitride layer in interfacial contact in interfacial contact with the front surface of the single crystal semiconductor handle substrate, wherein the textured semiconductor oxide layer comprises holes having sizes between about 5 nanometers and about 1000 nanometers, the textured semiconductor nitride layer comprises holes having sizes between about 5 nanometers and about 1000 nanometers, or the textured semiconductor oxynitride layer comprises holes having sizes between about 5 nanometers and about 1000 nanometers;
• a polycrystalline silicon layer in interfacial contact with the textured semiconductor oxide layer, the textured semiconductor nitride layer, or the textured semiconductor oxynitride layer;
• a dielectric layer in interfacial contact with the polycrystalline silicon layer;
• and
• a single crystal semiconductor device layer in interfacial contact with the dielectric layer,
• wherein the multilayer structure has wafer bow as measured by at least three points on the front surface of the semiconductor device layer and/or the back surface of the single crystal semiconductor handle substrate of less than about 80 micrometers.