Systems and methods to test a memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Lien Linus LU, Johnathan Tsung-Yung CHANG
Life of this patent
Estimating the term…
Abstract
A memory device includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; a plurality of row circuits respectively arranged along the plurality of rows; a plurality of column circuits respectively arranged along the plurality of columns; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing the pluralities of the row and column circuits.
Claims20
A memory device, comprising:
- a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively;
- and
- a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing one or more peripheral circuits coupled to the memory array.
A memory device, comprising:
- a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively;
- a plurality of row circuits respectively arranged along the plurality of rows;
- a plurality of column circuits respectively arranged along the plurality of columns;
- and
- a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing the pluralities of the row and column circuits.
A method, comprising:
- providing a write-once memory array comprising a plurality of write-once bit cells arranged along a plurality of rows and along a plurality of columns, respectively;
- determining respective locations of a first plurality of diagonal write-once bit cells of the write-once memory array based on respective numbers of the pluralities of rows and columns;
- and
- burning the first plurality of diagonal write-once bit cells for testing one or more peripheral circuits coupled to the write-once memory array.
Dependencies are inferred from the claim text.