Low Distortion Sample and Hold (S/H) Circuits and Associated Methods for Use with Analog-to-Digital Converters (ADCs)
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMei-Chen Chuang, Alan Roth
Life of this patent
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Abstract
A sample and hold (S/H) circuit includes a capacitor coupling a sample node to a first voltage and an input line carrying a signal from an input. The S/H circuit also can include one or more transistors coupling the input line to the sample node. The S/H circuit also can include a switch coupled to one or more sources or drains of the one or more transistors and to a second voltage. The S/H circuit also can include a hold circuit coupled to the switch and to one or more gates of the one or more transistors, the hold circuit configured to open, during a sample period, the input line between the input and the sample node.
Claims20
A sample and hold (S/H) circuit comprising:
- a capacitive element coupling a sample node to a first voltage;
- two transistors coupling an input line to the sample node;
- a switch coupled between a source of a first one of the two transistors and a drain of a second one of the two transistors, the switch also coupled to a second voltage;
- and
- a hold circuit coupled to the switch and to one or more gates of the one or more transistors, the hold circuit configured to open, during a sample period, the input line between the input and the sample node.
A sample and hold (S/H) circuit, comprising:
- a capacitive element coupling a sample node to a first voltage;
- an input line carrying a signal from an input;
- first and second transistors each coupling the input line to the sample node;
- a switch coupling a first node to a second voltage;
- and
- a hold circuit coupled to the switch and to respective gates of the first and second transistors, the hold circuit configured to open, during a sample period, the input line between the input and the sample node,
- wherein the first node lies between a source/drain of the first transistor and the drain of the second transistor, and
- wherein the switch is configured to open during the sample period.
A sample and hold (S/H) method, comprising:
- coupling an input line to a sample node by activating or deactivating respectively each gate of one or more transistors when a switch is off, the switch coupled between a source of a first one of the two transistors and a drain of a second one of the two transistors, the switch also coupled to a second voltage;
- and
- decoupling the input line from the sample node by respectively deactivating or activating each of the two gates when the switch is on.
Dependencies are inferred from the claim text.