Low Voltage Bit-Cell
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYen-Huei Chen, Mahmut Sinangil, Hung-Jen Liao, Tsung-Yung Chang
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Abstract
Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.
Claims20
A bit-cell, comprising:
- a write-port circuit activated by a first threshold voltage, the write-port circuit comprising:
- a first group of four transistors collectively forming a tri-state inverter, the first group comprising:
- a first transistor connected to a supply voltage, a first input of the first transistor connected to a write word-line signal;
- a second transistor having a second input;
- a third transistor having a third input connected to the second input;
- a fourth transistor connected to a ground signal, a fourth input of the fourth transistor connected to a write word-line complement signal;
- and
- a read-port circuit comprising a second group of four transistors, wherein the read-port circuit is activated by a second threshold voltage, and wherein the write-port circuit is coupled to the read-port circuit.
A system, comprising:
- a bit-cell, comprising:
- a write-port circuit comprising eight transistors;
- and
- a read-port circuit comprising four transistors;
- a first multiplexer circuit coupled to the write-port circuit, wherein the second multiplexer circuit is coupled to the first multiplexer circuit;
- a second multiplexer circuit coupled to the read-port circuit;
- and
- a power management circuit configured to minimize power leakage from the system.
The system of claim 15, wherein the first multiplexer circuit and the second multiplexer circuit are not provided with power during sleep mode and shut-down mode.
A method for writing to and reading from a bit cell, the method comprising:
- generating a voltage on a write bit line;
- activating a complementary switch in a write-port circuit based on a write word line signal;
- driving, based on the activating, a write bit line signal onto an internal bit line node;
- inverting, a voltage on the internal bit-line in node, the inverting based on a first threshold voltage;
- driving the inverted voltage onto the input of a tri-state inverter;
- inverting, by the tri-state inverter, the inverted voltage back to the write bit line signal, the inverting based on the write word line signal being greater than a first threshold voltage;
- and
- retaining a value on the internal bit line node based on a deactivation of the write word line signal.
Dependencies are inferred from the claim text.