Transpose static random access memory (sram) bit cells configured for horizontal and vertical read operations

A transpose static random access memory (SRAM) bit cell, comprising:

• a means for storing a data value formed over a substrate;
• a first means for accessing the data value;
• a second means for accessing the data value;
• a means for activating the first means for accessing the data value disposed in a first metal layer and having an axis disposed in a first direction;
• a means for receiving the data value via the first means for accessing the data value disposed in a second metal layer and having an axis disposed in a second direction substantially orthogonal to the first direction;
• a means for activating the second means for accessing the data value disposed in a third metal layer and having an axis disposed in the second direction;
• and
• a means for receiving the data value via the second means for accessing the data value disposed in a fourth metal layer and having an axis disposed in the first direction.

A method of performing a vertical read operation and a horizontal read operation on a transpose static random access memory (SRAM) bit cell, comprising:

• applying a voltage to a word line disposed in a first metal layer and having an axis disposed in a first direction, wherein the word line is electrically coupled to a horizontal read access transistor configured to access a data value stored by a first inverter cross-coupled with a second inverter;
• responsive to applying the voltage to the word line, sensing a voltage on a bit line disposed in a second metal layer and having an axis disposed in a second direction substantially orthogonal to the first direction, wherein the bit line is electrically coupled to the horizontal read access transistor;
• applying a voltage to a transpose word line disposed in a third metal layer and having an axis disposed in the second direction, wherein the transpose word line and electrically coupled to a gate node of a vertical read access transistor;
• and
• responsive to applying the voltage to the transpose word line, sensing the voltage on a transpose bit line disposed in a fourth metal layer and having an axis disposed in the first direction, wherein the transpose bit line is electrically coupled to the vertical read access transistor configured to access the data value stored by the first inverter cross-coupled with the second inverter.

A transpose static random access memory (SRAM) data array, comprising:

• a plurality of transpose SRAM bit cells organized into a plurality of transpose SRAM rows and a plurality of transpose SRAM columns, wherein each transpose SRAM bit cell of the plurality of transpose SRAM bit cells corresponds to a transpose SRAM row and a transpose SRAM column, and comprises:
• a first inverter and a second inverter formed over a substrate and cross-coupled such that the first inverter and the second inverter are configured to store a data value;
• a horizontal read access transistor formed over the substrate and comprising:
• a first node electrically coupled to an output node of the first inverter;
• a second node;
• and
• a gate node;
• and
• a vertical read access transistor formed over the substrate and comprising:
• a first node;
• a second node;
• and
• a gate node;
• a plurality of word lines, wherein each word line is disposed in a first metal layer, has an axis disposed in a first direction, and is electrically coupled to the gate node of the horizontal read access transistor of each transpose SRAM bit cell of a corresponding transpose SRAM row;
• a plurality of bit lines, wherein:
• each bit line is disposed in a second metal layer, has an axis disposed in a second direction substantially orthogonal to the first direction, and is electrically coupled to the second node of the horizontal read access transistor of each transpose SRAM bit cell of a corresponding transpose SRAM column;
• and
• the data value is indicated on the bit line in response to a voltage applied to the word line activating the horizontal read access transistor;
• a plurality of transpose word lines, wherein each transpose word line is disposed in a third metal layer, has an axis disposed in the second direction, and is electrically coupled to the gate node of the vertical read access transistor of each transpose SRAM bit cell of a corresponding transpose SRAM column;
• a plurality of transpose bit lines, wherein each transpose bit line is disposed in a fourth metal layer, has an axis disposed in the first direction, and is electrically coupled to the second node of the vertical read access transistor of each transpose SRAM bit cell of a corresponding transpose SRAM row;
• a plurality of horizontal sense amplifiers, wherein each horizontal sense amplifier of the plurality of horizontal sense amplifiers is electrically coupled to the bit line of each corresponding transpose SRAM column, and configured to sense the data value indicated on the bit line and generate a corresponding horizontal output data value;
• and
• a plurality of vertical sense amplifiers, wherein each vertical sense amplifier of the plurality of vertical sense amplifiers is electrically coupled to the transpose bit line of each corresponding transpose SRAM row, and configured to sense the data value indicated on the transpose bit line and generate a corresponding vertical output data value.