Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system

A method for transferring data from a first semiconductor device to a second semiconductor device, the method comprising:

• transferring preamble length information from the second semiconductor device to the first semiconductor device;
• storing the preamble length information in a register in the first semiconductor device;
• transferring a clock signal from the second semiconductor device to the first semiconductor device;
• switching between a Delay Lock Loop (DLL) selection mode in which a DLL circuit is activated and a DLL non-selection mode in which the DLL circuit is not activated;
• transferring, from the first semiconductor device to the second semiconductor device, a preamble having a duration specified by the preamble length information followed by a toggle signal having a burst length;
• and
• transferring, from the first semiconductor device to the second semiconductor device, data in synchronization with the toggle signal;
• wherein in the DLL selection mode, transferring the toggle signal further comprises:
• phase adjusting the toggle signal to the clock signal using the DLL circuit;
• and
• in the DLL non-selection mode, transferring the toggle signal comprises:
• transferring the toggle signal with the clock signal as a reference.

A method for transferring data from a first semiconductor device to a second semiconductor device comprising:

• transferring first preamble length information from the second semiconductor device to the first semiconductor device;
• storing the first preamble length information in a register in the first semiconductor device;
• transferring a clock signal from the second semiconductor device to the first semiconductor device;
• transferring a preamble having a duration specified by the first preamble length information, wherein the preamble is followed by a toggle signal having a burst length and the preamble is transferred from the first semiconductor device to the second semiconductor device, wherein the toggle signal is phase adjusted to the clock signal using a Delay Lock Loop (DLL) circuit;
• and
• transferring data in synchronization with the toggle signal from the first semiconductor device to second semiconductor device.