Memory devices for performing multiple write operations and operating methods thereof
AssigneeSamsung Electronics Co., Ltd.
InventorJong-pil Son
Life of this patent
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Abstract
A memory device for performing a data write operation based on a multiple write command, an operating method thereof, and an operating method of a memory controller are provided. An operating method of a memory device including a plurality of banks includes receiving a write command, and data and an address corresponding to the write command, decoding the received write command, and responsive to a result of the decoding indicating that the write command corresponds to a multiple write command, together writing the same data in two or more banks using an internal address generating operation that is based on the received address.
Claims23
An operating method of a memory device including a plurality of banks, the operating method comprising:
- receiving a write command, and data and an address corresponding to the write command;
- decoding the write command;
- and
- responsive to a result of the decoding indicating that the write command corresponds to a multiple write command, together writing the same data in two or more banks using an internal address generating operation that is based on the received address.
An operating method of a memory controller for controlling a memory device, the operating method comprising:
- receiving an initialization request for the memory device from a host;
- in response to the initialization request, generating a multiple write command to together write same initialization data in two or more banks of the memory device;
- transferring the multiple write command to the memory device;
- and
- transferring, to the memory device, a standard write command and an address indicating a position of a bank of the memory device in which data are to be written,
- wherein the multiple write command and the standard write command transferred to the memory device respectively comprise a plurality of fields,
- wherein a first combination of the plurality of fields of the multiple write command is different than a second combination of the plurality of fields of the standard write command.
(canceled)
A memory device comprising:
- a memory cell array including a plurality of banks;
- a command decoder configured to decode a write command and an address received from a memory controller to control a write operation on the plurality of banks;
- and
- a bank controller block configured to select one or more of the plurality of banks in which data is to be written,
- wherein, responsive to the command decoder decoding the write command as a standard write command, the data is written in one bank of the plurality of banks indicated by the address received from the memory controller, and
- wherein, responsive to the command decoder decoding the write command as a multiple write command, the data is together written in two or more banks of the plurality of banks of the memory cell array through an internal bank selecting operation.
-22. (canceled)
(canceled)
Dependencies are inferred from the claim text.