Memory circuit including tracking circuit

A memory circuit comprising:

• memory cells arranged in an array, each memory cell including a storage cell transistor corresponding to a predetermined transistor configuration;
• a first tracking bit line;
• a first tracking word line;
• a reference voltage node, a first terminal of the first tracking bit line being electrically coupled to the reference voltage node;
• and
• a tracking circuit electrically coupled between the first tracking word line and the reference voltage node, the tracking circuit including:
• a first set of first tracking cells, each first tracking cell including a first cell transistor corresponding to the predetermined transistor configuration, gate terminals of the first cell transistors being electrically coupled with the first tracking word line;
• and
• wherein:
• a driving capacity of the storage cell transistors of the memory cells has a storage cell statistical distribution under a predetermined operation setting which exhibits a weak bit current value;
• a driving capacity of the first cell transistors of the first set of tracking cells has a first tracking cell statistical distribution under the predetermined operation setting which exhibits a first strong bit current value;
• and
• a first quantity of the first tracking cells is sufficient to cause the first strong bit current value of the first tracking cell statistical distribution to be equal to or less than the weak bit current value of the storage cell statistical distribution.