Circuit for memory system and associated method
AssigneeRealtek Semiconductor Corp.
InventorsChih-Chia Chiu, Ruey-Beei Wu, Ting-Ying Wu, Wen-Shan Wang, GERCHIH CHOU
Life of this patent
Estimating the term…
Abstract
A circuit for a memory system including a plurality of memories, including: a plurality of connection traces coupled in series, each connection trace having a first end, and a second end coupled to a terminal of a memory of the plurality of memories; wherein an equivalent impedance of a first connection trace of the plurality of connection traces is different with the equivalent impedance of the second connection trace of the plurality of connection traces, the first connection trace being coupled to the second connection trace in series.
Claims20
A circuit for a memory system including a plurality of memories, comprising:
- a plurality of groups of connection traces coupled in series, each group of connection traces at least comprising a first connection trace and a second connection trace;
- each connection trace having a first end, and a second end coupled to a terminal of a memory of the plurality of memories;
- wherein an equivalent impedance of the first connection trace is different from an equivalent impedance of the second connection trace, and the first connection trace is coupled to the second connection trace in series.
A method for a memory system including a plurality of memories, comprising:
- coupling a plurality of groups of connection traces in series, each group of connection traces at least comprising a first connection trace and a second connection trace;
- each connection trace having a first end, and a second end coupled to a terminal of a memory of the plurality of memories;
- wherein an equivalent impedance of the first connection trace is different from an equivalent impedance of the second connection trace, and the first connection trace is coupled to the second connection trace in series.
Dependencies are inferred from the claim text.