Scanning trigger unit, gate driving circuit and method for driving the same and display apparatus

A method for driving a scanning trigger unit, wherein the scanning trigger unit comprises a clock signal terminal, a first signal input terminal, a fixed level signal terminal, a first input sub-circuit, an output sub-circuit, a first holding sub-circuit, and a signal output terminal, wherein the first input sub-circuit is connected to the first signal input terminal and a control node respectively, and is configured to provide a first valid signal to the control node according to a signal at the first signal input terminal, the output sub-circuit is connected to the fixed level signal terminal, the clock signal terminal, and the control node, and is configured to provide a second valid signal to the signal output terminal according to a signal at the control node and a signal at the clock signal terminal, and the first holding sub-circuit is connected to the fixed level signal terminal and the signal output terminal, and is configured to hold the second valid signal at the signal output terminal for a predetermined time,

• wherein the method comprises:
• in a first time period in which an input signal at the first signal input terminal is at a first level, and a signal at the clock signal terminal is at a second level, outputting, by the signal output terminal of the scanning trigger unit, a second level, and charging the first holding sub-circuit;
• in a second time period in which the input signal at the first signal input terminal is at a second level, charging, by the input sub-circuit, the control node in response to the input signal, so that level coupling of the output terminal is reduced;
• and
• in a third time period in which the input signal at the first signal input terminal is at the second level, discharging the first holding sub-circuit through the output sub-circuit, and outputting, by the signal output terminal of the scanning trigger unit, a first level.

A method for driving a gate driving circuit, wherein the gate driving circuit comprises a first scanning trigger unit, N stages of shift registers having an STV signal terminal connected to a signal output terminal of the first scanning trigger unit, where N is an integer greater than or equal to 2, a first signal line connected to a first signal input terminal of the first scanning trigger unit, and a first clock signal line connected to a clock signal terminal of the first scanning trigger unit,

• wherein the first scanning trigger unit comprises the clock signal terminal, the first signal input terminal, a fixed level signal terminal, a first input sub-circuit, an output sub-circuit, a first holding sub-circuit, and the signal output terminal, wherein the first input sub-circuit is connected to the first signal input terminal and a control node respectively, and is configured to provide a first valid signal to the control node according to a signal at the first signal input terminal, the output sub-circuit is connected to the fixed level signal terminal, the clock signal terminal, and the control node, and is configured to provide a second valid signal to the signal output terminal according to a signal at the control node and a signal at the clock signal terminal, and the first holding sub-circuit is connected to the fixed level signal terminal and the signal output terminal, and is configured to hold the second valid signal at the signal output terminal for a predetermined time,
• wherein the method comprises:
• in a triggering time period, providing a signal having a first level through the first signal line, and providing a clock signal having a second level through the first clock signal line;
• in a holding time period, providing a signal having a second level through the first signal line, and providing a clock signal having a first level through the first clock signal line;
• in a driving time period, providing a signal having the second level through the first signal line, and providing a signal having the first level and a signal having the second level periodically through the first clock signal line;
• and
• in a resetting time period, providing a signal having the first level through the first signal line, and providing a clock signal having the first level through the first clock signal line.