A gate driver on array (GOA) circuit applying to a liquid crystal panel, the GOA circuit comprising a plurality of cascaded GOA unit circuits, an nth stage GOA unit circuit comprising:
- a clock signal source, configured to supply a current-stage clock signal, the clock signal comprising a first high voltage level and a first low voltage level;
- a constant voltage supply, configured to supply a second low voltage level;
- a pull-up control circuit, configured to receive an (n−1)th stage scanning signal and generate a current-stage scanning voltage level signal under a control of an (n−1)th stage cascade signal;
- a pull-up circuit, configured to output the current-stage clock signal to an output terminal of a current-stage scanning signal under a control of the current-stage scanning voltage level signal;
- a downlink circuit, configured to receive the current-stage clock signal and generate an nth stage cascade signal under a control of the current-stage scanning voltage level signal;
- a pull-down circuit, configured to output the second low voltage level supplied by the constant voltage supply to the output terminal of the current-stage scanning signal according to an (n+1)th stage scanning signal;
- a pull-down maintaining circuit, configured to maintain the current-stage scanning voltage level signal at a low voltage level;
- a bootstrap capacitor, configured to generate the current-stage scanning voltage level signal at a high voltage level;
- and
- a conducting control circuit, configured to control conducted time when the pull-down maintaining circuit receives a square-wave signal of the TFT, wherein the conducting control circuit comprises a first thin film transistor (TFT) and a second TFT;
- a gate of the first TFT receives the current-stage clock signal;
- a source of the first TFT receives a first square-wave signal;
- a drain of the first TFT is electrically connected to the pull-down maintaining circuit;
- a gate of the second receives the current-stage clock signal;
- a source of the second TFT receives a second square-wave signal;
- a drain of the second TFT is electrically connected to the pull-down maintaining circuit;
- and
- a beveled control signal circuit, configured to output a beveled control signal under the control of the current-stage clock signal;
- the pull-up circuit configured to output the beveled control signal to the output terminal of the current-stage scanning signal under the control of the current-stage scanning voltage level signal;
- the downlink circuit configured to receive the beveled control signal and generate a second stage cascade signal under the control of the current-stage scanning voltage level signal;
- the clock signal source electrically connected to the beveled control signal circuit;
- the beveled control signal circuit electrically connected to the pull-up circuit and the downlink circuit;
- wherein an output terminal of the pull-up control circuit is electrically connected to the pull-up circuit, the downlink circuit, the pull-down circuit, the pull-down maintaining circuit, and the bootstrap capacitor;
- the constant voltage supply is electrically connected to the pull-down maintaining circuit and the pull-down circuit;
- the clock signal source is electrically connected to the pull-up circuit, the downlink circuit, and the conducting control circuit;
- the conducting control circuit is electrically connected to the pull-down maintaining circuit.