Array substrate and display panel
AssigneeWuhan China Star Optoelectronics Technology Co., Ltd.
InventorsTingting ZHANG, Cong WANG
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to an array substrate and a display panel. The array substrate includes a plurality of scanning lines and a plurality of data lines intersecting with each other to form a plurality of pixel cells. The pixel cells are divided into the pixel cells within a first area and the pixel cells within a second area along the scanning lines. Each of the pixel cells within the second area includes a first thin film transistor (TFT) and a control unit connected to the first TFT. The control unit is configured to reduce a pixel voltage of the pixel cell where the first TFT is configured. As such, the display panel may display images uniformly, and display performance of the display panel may be improved.
Claims16
An array substrate, comprising:
- a plurality of scanning lines;
- a plurality of data lines, wherein the data lines and the scanning lines respectively intersect with each other to form a plurality of pixel cells;
- wherein the pixel cells are divided into the pixel cells within a first area and the pixel cells within a second area along the scanning lines, and a distance between the first area and an input end of scanning signals is less than a distance between the second area and the input end of the scanning signals;
- each of the pixel cells within the second area comprises a first thin film transistor (TFT) and a control unit connected to the first TFT, the control unit is configured to reduce a pixel voltage of the pixel cell where the first TFT is configured, and each of the pixel cells within the first area comprises a second TFT;
- the control unit comprises a third TFT and a first capacitor, a drain of the third TFT connects to a pixel electrode of the pixel cell where the third TFT is configured, and a gate of the third TFT connects to a scanning line at a next row;
- and
- each of the pixel cells within the first area comprises a fourth TFT, a gate of the fourth TFT connects to the scanning line at the next row, a source of the fourth TFT is grounded via a second capacitor, and a drain of the fourth TFT is grounded via a third capacitor.
8-16. (canceled)
A display panel, comprising:
- an array substrate comprising:
- a plurality of scanning lines;
- a plurality of data lines, wherein the data lines and the scanning lines respectively intersect with each other to form a plurality of pixel cells;
- wherein the pixel cells are divided into the pixel cells within a first area and the pixel cells within a second area along the scanning lines, and a distance between the first area and an input end of scanning signals is less than a distance between the second area and the input end of the scanning signals;
- each of the pixel cells within the second area comprises a first TFT and a control unit connected to the first TFT, the control unit is configured to reduce a pixel voltage of the pixel cell where the first TFT is configured, and each of the pixel cells within the first area comprises a second TFT;
- the control unit comprises a third TFT and a first capacitor, a drain of the third TFT connects to a pixel electrode of the pixel cell where the third TFT is configured, and a gate of the third TFT connects to a scanning line at a next row;
- each of the pixel cells within the first area comprises a fourth TFT, a gate of the fourth TFT connects to the scanning line at the next row, a source of the fourth TFT is grounded via a second capacitor, and a drain of the fourth TFT is grounded via a third capacitor.
(canceled)
Dependencies are inferred from the claim text.