Level shift circuit, control method thereof, display device and drive circuit thereof

A control method of a level shift circuit which comprises a level shift sub-circuit and at least one detection sub-circuit;

• the level shift sub-circuit is connected to at least two signal input ends and at least two signal output ends respectively, and each detection sub-circuit is connected to two signal output ends and the level shift sub-circuit respectively, comprising:
• detecting whether signals output by the two signal output ends that are connected to each detection sub-circuit meet a normal output condition or not;
• and
• stopping outputting signals to two signal output ends that are connected to any of the detection sub-circuit when detecting that the signals output by two signal output ends that are connected to any of the detection sub-circuit do not meet the normal output condition.

A drive circuit of a display device, comprising a gate drive circuit and a level shift circuit, wherein the level shift circuit comprises a level shift sub-circuit and at least one detection sub-circuit:

• the level shift sub-circuit is connected to at least two signal input ends and at least two signal output ends respectively and configured to convert the level of an input signal that is provided by each signal input end and then to output the level-converted input signal to the corresponding signal output end, each signal input end corresponding to one of the signal output ends;
• each detection sub-circuit is connected to two signal output ends and a feedback signal input end of the level shift sub-circuit respectively and configured to output a feedback signal with a first level to the level shift sub-circuit when detecting that signals output by the two signal output ends connected thereto do not meet a normal output condition;
• the level shift sub-circuit is further configured to stop outputting signals to two signal output ends that are connected to any of the detection sub-circuits when detecting the feedback signal with the first level sent by any of the detection sub-circuits;
• and
• the at least two signal output ends are connected to the gate drive circuit and configured to provide the gate drive circuit with a clock signal.