Area-efficient implementations of graphics instructions

An apparatus comprising a graphics subsystem, the graphics subsystem including:

• a translation lookaside buffer (TLB);
• and
• a data port controller to control the TLB, the data port controller including:
• an incoming request pipeline to receive an incoming request with virtual address and generate a response,
• an incoming response pipeline to receive the response and generate a cache request, and
• an invalidation flow pipeline.

A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:

• handling received graphical data, including one or more of the following:
• a first process for receiving a message including read data in a raw memory format, and assembling the read data into register format upon all cache line requests for the message being received;
• a second process for assembling memory read-return data for media block instructions into shader register format, including storing of valid bytes from a cache fragment into a register;
• or
• a third process for remapping scatter or gather instructions to untyped surface instruction types.

A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:

• receiving an incoming request with virtual address at a data port, the data port including a translation lookaside buffer (TLB);
• generating a response for the request;
• receiving the response and generating a cache request;
• and
• processing one or more invalid requests.