Integrated circuit layout methods, structures, and systems
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Hsiang HUANG, Sheng-Hsiung CHEN, Fong-Yuan CHANG
Life of this patent
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Abstract
A method of generating a layout of an IC includes identifying a target pin in a first cell in an IC layout, the first cell being adjacent to a second cell and sharing a boundary with the second cell, and determining whether or not the target pin is capable of being extended into the second cell. Based on a determination that the target pin is capable of being extended into the second cell, the target pin is modified to include an extension into the second cell, the target pin thereby crossing the shared boundary. At least one of the identifying, determining, or modifying is executed by a processor of a computer.
Claims21
A method of generating a layout of an integrated circuit (IC), the method comprising:
- identifying a target pin in a first cell in an IC layout, the first cell being adjacent to a second cell and sharing a boundary with the second cell;
- determining whether or not the target pin is capable of being extended into the second cell;
- and
- based on a determination that the target pin is capable of being extended into the second cell, modifying the target pin to include an extension into the second cell, the target pin thereby crossing the shared boundary,
- wherein at least one of the identifying, determining, or modifying is executed by a processor of a computer.
9-14. (canceled)
An integrated circuit (IC) layout generation system comprising:
- a processor;
- and
- a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the system to:
- receive a first cell, the first cell comprising a first metal zero structure;
- receive a second cell;
- place the first cell adjacent to the second cell in an IC layout, the first cell and the second cell thereby sharing a boundary;
- receive a metal zero spacing rule;
- based on the metal zero spacing rule, extend the first metal zero structure across the border and into the second cell;
- and
- generate a layout of a semiconductor structure based on the first cell and the second cell.
A method of generating a layout of an integrated circuit (IC), the method comprising:
- calculating a length of a target pin extension for a target pin in a first cell in an IC layout, the first cell being adjacent to a second cell and sharing a boundary with the second cell;
- comparing a length of a gap between the target pin extension and an identified feature of the second cell to a minimum spacing rule;
- and
- based on a determination that the gap is larger than the minimum spacing rule, modifying the target pin to include the target pin extension into the second cell, the target pin thereby crossing the shared boundary,
- wherein at least one of the calculating, comparing, or modifying is executed by a processor of a computer.
Dependencies are inferred from the claim text.