Methods and apparatus for reducing reliability degradation on an integrated circuit
AssigneeIntel Corporation
InventorsNing Cheng, Xiangyong Wang, Mahesh A. Iyer
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntel Corporation
InventorsNing Cheng, Xiangyong Wang, Mahesh A. Iyer
Estimating the term…
An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.
A method of using integrated circuit design tools to implement a given circuit design on an integrated circuit, the method comprising:
An integrated circuit, comprising:
A non-transitory computer-readable storage medium comprising instructions for:
Dependencies are inferred from the claim text.