Methods and apparatuses for reducing power consumption in a pattern recognition processor
AssigneeMicron Technology, Inc.
InventorsHarold B Noyes, David R. Brown
Life of this patent
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Abstract
Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.
Claims20
A system, comprising:
- a pattern recognition processor comprising:
- a plurality of blocks, wherein each block of the plurality of blocks comprises a plurality of programmable elements, wherein each programmable element of the plurality of programmable elements comprises a plurality of memory cells to analyze data;
- and
- a power control circuit coupled to a second block of the plurality of blocks, wherein the power control circuit is configured to activate the second block before analysis of the data progresses from a first block of the plurality of blocks to the second block.
A system, comprising;
- a pattern recognition processor, comprising:
- a plurality of blocks, wherein each block of the plurality of blocks comprises a plurality of programmable elements, wherein each programmable element of the plurality of programmable elements comprises a plurality of memory cells usable in an analysis of data;
- and
- a power control circuit coupled to a first block of the plurality of blocks, wherein the power control circuit is configured to activate the first block to analyze the data when the data is identified as comprising a first type of data.
A system, comprising;
- a pattern recognition processor, comprising:
- a plurality of blocks, wherein each block of the plurality of blocks comprises a plurality of programmable elements, wherein each programmable element of the plurality of programmable elements comprises a plurality of memory cells to analyze data;
- and
- a power control circuit coupled to a first block of the plurality of blocks, wherein the power control circuit is configured to deactivate the first block to prevent the first block from analyzing the data based upon a search criteria of the pattern recognition processor.
Dependencies are inferred from the claim text.