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US 2019/0095496 A1Published application
Devices, systems, and methods to synchronize simultaneous dma parallel processing of a single data stream by multiple devices
AssigneeMicron Technology, Inc.
InventorHarold B Noyes
Life of this patent
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Abstract
Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.
Claims20
An electronic device, comprising:
- a plurality of pattern-recognition processors, wherein each pattern-recognition processor of the plurality of pattern-recognition processors comprises a plurality of programmable elements, wherein each programmable element of the plurality of programmable elements comprises a plurality of memory cells configured to be selectively utilized in an analysis of data;
- and
- a control bus coupled to each pattern-recognition processor of the plurality of pattern-recognition processors, wherein the control bus is configured to transmit a control signal to a first pattern-recognition processor of the plurality of pattern-recognition processors to control movement of data from the data stream into and out of the first pattern-recognition processor.
An electronic device, comprising:
- a plurality of pattern-recognition processors configured to simultaneously process a data stream, wherein each pattern-recognition processor of the plurality of pattern-recognition processors comprises a plurality of programmable elements, wherein each programmable element of the plurality of programmable elements comprises a plurality of memory cells configured to be selectively utilized in processing of the data stream;
- and
- a control bus coupled to each pattern-recognition processor of the plurality of pattern-recognition processors, wherein the control bus is configured to transmit a respective control signal to each pattern-recognition processor of the plurality of pattern-recognition processors to control movement of data from the data stream into and out of each pattern-recognition processor of the plurality of pattern-recognition processors.
A system, comprising:
- a processing unit adapted to generate information related to processing of a data stream;
- and
- a pattern-recognition cluster comprising:
- a plurality of pattern-recognition processors, wherein each pattern-recognition processor of the plurality of pattern-recognition processors comprises a plurality of programmable elements, wherein each programmable element of the plurality of programmable elements comprises a plurality of memory cells configured to be selectively utilized in an analysis of data;
- and
- a control bus coupled to each pattern-recognition processor of the plurality of pattern-recognition processors, wherein the control bus is configured to transmit a control signal to a first pattern-recognition processor of the plurality of pattern-recognition processors to control movement of data from the data stream into and out of the first pattern-recognition processor.
3 more elements
Dependencies are inferred from the claim text.