US 2019/0095399 A1 · ASSYMETRIC ALLOCATION OF SRAM AND DATA LAYOUT FOR EFFICIENT MATRIX MULTIPLICATION

Abstract

Techniques are described herein for performing efficient matrix multiplication in architectures with scratchpad memories or associative caches using asymmetric allocation of space for the different matrices. The system receives a left matrix and a right matrix. In an embodiment, the system allocates, in a scratchpad memory, asymmetric memory space for tiles for each of the two matrices as well as a dot product matrix. The system proceeds with then performing dot product matrix multiplication involving the tiles of the left and the right matrices, storing resulting dot product values in corresponding allocated dot product matrix tiles. The system then proceeds to write the stored dot product values from the scratchpad memory into main memory.

Claims22

Dependent claims

A method for performing matrix multiplication between a left matrix, A, and a right matrix, B, in a processor, comprising:

receiving a left matrix, A, and a right matrix, B, wherein matrix A has m rows and n columns, and matrix B has n rows and p columns, and wherein matrix B is smaller than matrix A;
allocating, in a scratchpad memory that is associated with the processor, asymmetric memory space for a tile each, of matrix A, matrix B, and a dot product matrix C;
performing a dot product matrix multiplication involving one or more tiles of matrix A and corresponding tiles of matrix B, wherein the dot product values are stored in corresponding tiles of matrix C;
and
writing out the stored dot product values into main memory.

2 more elements

One or more non-transitory storage media storing instructions, which when executed by one or more computing devices cause:

receiving a left matrix, A, and a right matrix, B, wherein matrix A has m rows and n columns, and matrix B has n rows and p columns, and wherein matrix B is smaller than matrix A;
allocating, in a scratchpad memory that is associated with the processor, asymmetric memory space for a tile each, of matrix A, matrix B, and a dot product matrix C;
performing a dot product matrix multiplication involving one or more tiles of matrix A and corresponding tiles of matrix B, wherein the dot product values are stored in corresponding tiles of matrix C;
and
writing out the stored dot product values into main memory.

2 more elements

Dependencies are inferred from the claim text.

Assymetric allocation of sram and data layout for efficient matrix multiplication

Life of this patent

Assymetric allocation of sram and data layout for efficient matrix multiplication

Life of this patent

Abstract

Claims22