Processors, methods, and systems for a memory fence in a configurable spatial accelerator

A method comprising:

• receiving an input of a dataflow graph comprising a plurality of nodes;
• overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements;
• performing a plurality of operations of the dataflow graph with the interconnect network and the plurality of processing elements, each by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements;
• and
• performing a fence operation to establish a memory fence between a first operation and a second operation of the plurality of operations.

A system comprising:

• a system memory;
• and
• a processor including:
• a plurality of processing elements;
• an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as one of a plurality of dataflow operators in the plurality of processing elements, and the plurality of processing elements are to perform a plurality of operations, each by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements;
• and
• a fence manager to manage a memory fence between a first operation and a second operation of the plurality of operations, wherein the first operation and the second operation are to access the system memory.