US 2019/0095365 A1 · TECHNIQUES FOR REDUCING ACCELERATOR-MEMORY ACCESS COSTS IN PLATFORMS WITH MULTIPLE MEMORY CHANNELS

Abstract

Methods and apparatus for reducing accelerator-memory access costs in platforms with multiple memory channels. The apparatus includes a computing platform having multiple accelerators and multiple memory devices accessed via a plurality of memory channels. Jobs are submitted via software running on the computing platform to access a function to be offloaded to an accelerator. Under the offloaded function, the accelerator accesses one or more buffers that collectively requiring access via multiple memory channels among the plurality of memory channels. Accelerators having an available instance of the function are identified, and an aggregate cost for accessing the one or more buffers via the multiple memory channels are calculated for each of the accelerators. The accelerator with the least aggregate cost is then selected to offload the function to. New Instruction Set Architecture (ISA) instructions are also disclosed to identify memory pages and memory channels used for buffers.

Claims25

Dependent claims

A method performed on a computing platform including a plurality of accelerators and a plurality of memory devices accessed by a plurality of memory channels, the method comprising:

in response to a job submission to access a function to be offloaded to an accelerator, the function to access one or more buffers, the one or more buffers collectively requiring access via multiple memory channels among the plurality of memory channels,
identifying accelerators with an available instance of the function;
calculating, for each identified accelerator, an aggregate cost for accessing the one or more buffers via the multiple memory channels;
and
selecting the accelerator with the least aggregate cost to offload the function to.

2 more elements

A multi-socket computing platform having a Non-Uniform Memory Access (NUMA) Architecture, comprising:

a plurality of NUMA nodes, each including,
a processor comprising a plurality of components including,
a plurality of processor cores;
at least one memory controller having a plurality of memory channels;
a socket-to-socket interface;
at least one accelerator;
and
internal interconnection circuitry coupling the plurality of components in communication;
a plurality of memory devices, communicatively coupled to plurality of memory channels on the processor;
and
socket-to-socket interconnection circuitry to enable communication between pairs of processors;
wherein, upon operation the multi-socket computing platform is configured to,
in response to a job submission via software running on the multi-socket computing platform to access a function to be offloaded to an accelerator, the function to access one or more buffers, the one or more buffers collectively requiring access via multiple memory channels among the plurality of memory channels,
identify accelerators with an available instance of the function;
calculate, for each identified accelerator, an aggregated cost for accessing the one or more buffers that are identified via the multiple memory channels;
and
select the accelerator with the least aggregate cost to offload the function to.

14 more elements

Dependencies are inferred from the claim text.

Techniques for reducing accelerator-memory access costs in platforms with multiple memory channels

Life of this patent

Techniques for reducing accelerator-memory access costs in platforms with multiple memory channels

Life of this patent

Abstract

Claims25