Sorting Memory Address Requests for Parallel Memory Access

A method of identifying a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address comprising:

• performing a comparison of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset;
• at each of a plurality of combination logic units:
• receiving a predetermined selection of bits of the binary classification dataset;
• and sorting its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset;
• and
• selecting between bits belonging to different intermediary binary strings to generate a binary output identifying a set of output memory addresses containing at least one address in the identified subset.

A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an apparatus configured to identify a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address, the apparatus comprising:

• a comparator block configured to perform comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset;
• a plurality of combination logic units, each combination logic unit being configured to:
• receive a predetermined selection of bits of the binary classification dataset;
• and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset;
• and
• output generating logic configured to select between bits belonging to different intermediary binary strings to generate a binary output identifying a set of output memory addresses containing at least one address in the identified subset.