Hardware support for static mode of protected memory management on flexibly-convertible enclave platform

A system comprising:

• a processor core;
• and
• a memory controller coupled between the processor core and main memory;
• and
• wherein the processor core is to:
• execute a patch-load instruction to retrieve, from a predetermined area of the main memory, memory protection metadata and a memory range of reserved memory within the main memory, wherein the reserved memory is not flexibly convertible to enclave pages;
• access a bit in an architectural control register, wherein a value of the bit is to indicate whether an operating system is capable of management of flexibly-convertible enclave pages within the main memory;
• and
• activate, using the memory protection metadata and the memory range, a mode of protected memory management for the processor core in response to the value of the bit in the architectural control register.

A method comprising:

• writing to a predetermined area of main memory, via execution of a basic input-output system (BIOS) by a processor core, memory protection metadata and first information to delineate a memory range of the main memory allocable for conversion to enclave pages;
• writing to the predetermined area of the main memory, via execution of the BIOS by the processor core, second information to delineate sub-sets of the memory range allocated for reserved memory, wherein the reserved memory is not flexibly convertible to enclave pages;
• retrieving from the predetermined area of the main memory, by the processor core executing a patch-load instruction, the memory protection metadata, the first information, and the second information;
• retrieving, by the processor core, a bit from an architectural control register, wherein a value of the bit is to indicate whether an operating system is capable of management of flexibly-convertible enclave pages;
• and
• activating, by the processor core using the memory protection metadata and one of the first information or the second information, a mode of protected memory management for the processor core in response to the value of the bit in the architectural control register.