US 2019/0095351 A1 · TECHNOLOGIES FOR A MEMORY ENCRYPTION ENGINE FOR MULTIPLE PROCESSOR USAGES

Abstract

Technologies for secure memory usage include a computing device having a processor that includes a memory encryption engine and a memory device coupled to the processor. The processor supports multiple processor usages, such as secure enclaves, system management firmware, and a virtual machine monitor. The memory encryption engine is configured to protect a memory region stored in the memory device for a processor usage. The memory encryption engine restricts access to one or more configuration registers to a trusted code base of the processor usage. The processor executes the processor usage and the memory encryption engine protects contents of the memory region during execution. The memory encryption engine may access integrity metadata based on the address of the protected memory region. The memory encryption engine may prepare top-level counter metadata for entering a low-power state. Other embodiments are described and claimed.

Claims25

Dependent claims

A computing device for secure memory usage, the computing device comprising:

a processor that includes a memory encryption engine, wherein the processor supports a plurality of processor usages;
a memory device coupled to the processor;
and
configuration logic to configure the memory encryption engine to protect a first memory region for a first processor usage of the plurality of processor usages, wherein the first memory region is stored by the memory device;
wherein the processor is to execute the first processor usage in response to configuration of the memory encryption engine;
and
wherein the memory encryption engine is to protect contents of the first memory region in response to execution of the first processor usage.

4 more elements

One or more computer-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a computing device to:

configure a memory encryption engine of a processor of the computing device to protect a first memory region for a first processor usage of a plurality of processor usages supported by the processor, wherein the first memory region is stored by a memory device coupled to the processor;
execute the first processor usage in response to configuring the memory encryption engine;
and
protect, by the memory encryption engine, contents of the first memory region in response to executing the first processor usage.

1 more element

Dependencies are inferred from the claim text.

Technologies for a memory encryption engine for multiple processor usages

Life of this patent

Technologies for a memory encryption engine for multiple processor usages

Life of this patent

Abstract

Claims25