Apparatus, system, and method to determine a cache line in a first memory device to be evicted for an incoming cache line from a second memory device
AssigneeIntel Corporation
InventorsHelia NAEIMI, Qi ZENG
Life of this patent
Estimating the term…
Abstract
Provided are an apparatus, system, and method to determine a cache line in a first memory device to be evicted for an incoming cache line in a second memory device. An incoming cache line is read from the second memory device. A plurality of cache lines in the first memory device are processed to determine an eviction cache line of the plurality of cache lines in the first memory device having a least number of bits that differ from corresponding bits in the incoming cache line. Bits from the incoming cache line that are different from the bits in the eviction cache line are written to the eviction cache line in the first memory device.
Claims25
An apparatus to determine a cache line in a first memory device to evict for an incoming cache line from a second memory device, comprising:
- a memory management unit to:
- read an incoming cache line from the second memory device;
- process a plurality of cache lines in the first memory device to determine an eviction cache line of the plurality of cache lines in the first memory device having a least number of bits that differ from corresponding bits in the incoming cache line;
- and
- write bits from the incoming cache line that are different from the bits in the eviction cache line to the eviction cache line in the first memory device.
A system, comprising:
- a first memory device;
- a second memory device;
- a memory management unit to:
- read an incoming cache line from the second memory device;
- process a plurality of cache lines in the first memory device to determine an eviction cache line of the plurality of cache lines in the first memory device having a least number of bits that differ from corresponding bits in the incoming cache line;
- and
- write bits from the incoming cache line that are different from the bits in the eviction cache line to the eviction cache line in the first memory device.
A method for determining a cache line to evict from a first memory device for an incoming cache line from a second memory device, comprising:
- reading an incoming cache line from the second memory device;
- processing a plurality of cache lines in the first memory device to determine an eviction cache line of the plurality of cache lines in the first memory device having a least number of bits that differ from corresponding bits in the incoming cache line;
- and
- writing bits from the incoming cache line that are different from the bits in the eviction cache line to the eviction cache line in the first memory device.
Dependencies are inferred from the claim text.