System control using sparse data
AssigneeApple Inc.
InventorsMichael R. Seningen, Ben D. Jarrett, Edward M. McCombs, Greg M. Hess
Life of this patent
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Abstract
A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.
Claims20
A system, comprising:
- a memory circuit including a plurality of banks;
- a sparse array circuit, including a plurality of entries, wherein a given entry of the plurality of entries corresponds to an address location in the memory circuit, in which a sparse data pattern is stored, wherein the sparse array circuit is configured to:
- receive first information indicative of a request to perform a read operation, wherein the first information includes a first address;
- compare the first address to at least one entry of the plurality of entries;
- and
- in response to a determination that the first address matches a particular entry of the plurality of entries, generate first and second control signals, wherein the memory circuit is further configured to disable the read operation based upon the first control signal;
- and
- a data control circuit configured to transmit the sparse data pattern on a bus coupled to the memory circuit based on the second control signal.
A method, comprising:
- receiving, by a memory, information indicative of a request to perform a read operation, wherein the information includes an address;
- comparing the address to at least one entry of a plurality of entries included in a sparse array circuit, wherein a given entry of the plurality of entries corresponds to an address location in the memory, in which a sparse data pattern is stored;
- and
- in response to determining that the address matches a particular entry of the plurality of entries:
- disabling the read operation;
- and
- transmitting, by a data control circuit, the sparse data pattern on a bus coupled to the memory.
A non-transitory computer-readable storage medium having design information stored thereon, wherein the design information specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the hardware integrated circuit according to the design information, wherein the design information specifies that the hardware integrated circuit comprises:
- a memory circuit including a plurality of banks;
- a sparse array circuit, including a plurality of entries, wherein a given entry of the plurality of entries corresponds to an address location in the memory circuit, in which a sparse data pattern is stored, wherein the sparse array circuit is configured to:
- receive first information indicative of a request to perform a read operation, wherein the first information includes a first address;
- compare the first address to at least one entry of the plurality of entries;
- and
- in response to a determination that the first address matches a particular entry of the plurality of entries, generate first and second control signals;
- and
- wherein the memory circuit is further configured to disable the read operation based upon the first control signal;
- and
- a data control circuit configured to transmit the sparse data pattern on a bus coupled to the memory circuit based on the second control signal.
Dependencies are inferred from the claim text.