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US 2019/0095335 A1Published application
Opportunistic increase of ways in memory-side cache
AssigneeIntel Corporation
InventorRuchira Sasanka
Life of this patent
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Abstract
A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.
Claims20
A processor comprising:
- a processor core;
- and
- a cache controller coupled to the processor core, the cache controller to allocate, for a memory, a plurality of cache entries in a cache;
- and
- wherein the processor core is to:
- detect an amount of the memory installed in one or more memory sockets of a computing system;
- determine a maximum allowable amount of memory for the computing system according to maximum capacity of the one or more memory sockets;
- and
- responsive to detecting less than the maximum allowable amount of memory installed in the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.
6 more elements
A system comprising:
- a processor;
- a cache controller coupled to the processor;
- and
- a cache coupled to the cache controller, wherein the cache controller is to allocate, for a memory, a plurality of cache entries in the cache;
- and
- wherein the processor is to:
- detect an amount of the memory installed in one or more memory sockets of the system;
- determine a maximum allowable amount of memory for the system according to maximum capacity of the one or more memory sockets;
- and
- responsive to detecting less than the maximum allowable amount of memory installed in the system:
- direct the cache controller to flush the cache;
- and
- direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.
10 more elements
A method comprising:
- allocating, by a multi-core processor of a computing system and for a memory, a plurality of cache entries in a cache of the memory;
- detecting, by the multi-core processor, an amount of the memory installed in one or more memory sockets of the computing system;
- determining, by the multi-core processor, a maximum allowable amount of memory for the computing system according to maximum capacity of the one or more memory sockets;
- and
- increasing, by the multi-core processor, a number of ways of the cache in which to allocate the plurality of cache entries, wherein the increasing is in response to detecting less than the maximum allowable amount of memory installed in the computing system.
2 more elements
Dependencies are inferred from the claim text.