US 2019/0095334 A1 · SECURE MEMORY REPARTITIONING TECHNOLOGIES

Abstract

Secure memory repartitioning technologies are described. Embodiments of the disclosure may include a processing device including a processing core and a memory controller coupled between the processor core and a memory device. The memory device includes a memory range including a section of convertible pages that are convertible to secure pages or non-secure pages. The processor core is to receive a non-secure access request to a page in the memory device, responsive to a determination, based on one or more secure state bits in one or more secure state bit arrays, that the page is a secure page, insert an abort page address into a translation lookaside buffer, and responsive to a determination, based on the one or more secure state bits in the one or more secure state bit arrays, that the page is a non-secure page, insert the page into the translation lookaside buffer.

Claims20

Dependent claims

A processing device comprising:

a processing core;
and
a memory controller coupled between the processor core and a memory device, wherein the memory device comprises a memory range comprising a section of convertible pages that are convertible to secure pages or non-secure pages, and wherein the processor core is to:
receive a non-secure access request to a page in the memory device;
responsive to a determination, based on one or more secure state bits in one or more secure state bit arrays, that the page is a secure page, insert an abort page address into a translation lookaside buffer;
and
responsive to a determination, based on the one or more secure state bits in the one or more secure state bit arrays, that the page is a non-secure page, insert the page into the translation lookaside buffer.

4 more elements

A system comprising:

a memory device to store pages;
and
a processing device operably coupled to the memory device, the processing device comprising a prefetcher and a memory encryption engine, and the processing device to:
responsive to receiving, from the prefetcher at the memory encryption engine, a first secure access request to a secure page of the pages, provide access to the secure page to the prefetcher;
execute an instruction to convert the secure page to a non-secure page;
responsive to receiving a non-secure write request to the non-secure page from an application, write to the non-secure page to create a modified non-secure page in the memory device;
and
responsive to receiving, from the prefetcher, a second secure access request to the modified non-secure page, return, via the memory encryption engine based on at least one counter set to an initialization value, a fixed pattern of data to the prefetcher to prevent system shutdown.

5 more elements

Dependencies are inferred from the claim text.

Secure memory repartitioning technologies

Life of this patent

Secure memory repartitioning technologies

Life of this patent

Abstract

Claims20