Back to results
US 2019/0095332 A1Published application
Near memory miss prediction to reduce memory access latency
AssigneeIntel Corporation
InventorsZhe Wang, Zeshan A. Chishti, Alaa R. Alameldeen, Rajat Agarwal
Life of this patent
Estimating the term…
Abstract
Systems, apparatuses and methods may provide for technology to maintain a prediction table that tracks missed page addresses with respect to a first memory. If an access request does not correspond to any valid page addresses in the prediction table, the access request may be sent to the first memory. If the access request corresponds to a valid page address in the prediction table, the access request may be sent to the first memory and a second memory in parallel, wherein the first memory is associated with a shorter access time than the second memory.
Claims25
A semiconductor package apparatus comprising:
- one or more substrates;
- and
- logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed functionality logic hardware, the logic coupled to the one or more substrates configured to:
- maintain a prediction table that tracks missed page addresses with respect to a first memory,
- send, if an access request does not correspond to any valid page address in the prediction table, the access request to the first memory,
- send, if the access request corresponds to a valid page address in the prediction table, the access request to the first memory and a second memory in parallel, wherein the first memory is associated with a shorter access time than the second memory,
- update, if the access request corresponds to the valid page address in the prediction table, one or more replacement policy bits of a prediction table entry associated with the valid page address to maintain the prediction table,
- detect a tag hit in the first memory, wherein the tag hit is to be associated with the access request,
- clear, if the access request corresponds to the valid page address in the prediction table, a valid bit of the prediction table entry associated with the valid page address in response to the tag hit,
- detect hits with respect to the first memory, wherein each of the hits does not correspond to any valid page address in the prediction table, and
- prevent the prediction table from tracking the hits by a bypass of one or more of any entry allocation in the prediction table to the hits or any bit allocation in the prediction table to the hits.
8 more elements
A system comprising:
- a processor to issue an access request;
- a first memory;
- a second memory, wherein the first memory is associated with a shorter access time than the second memory;
- and
- a memory controller coupled to the processor, the first memory and the second memory, the memory controller configured to:
- maintain a prediction table that tracks missed page addresses with respect to the first memory,
- send, if the access request does not correspond to any valid page address in the prediction table, the access request to the first memory,
- send, if the access request corresponds to a valid page address in the prediction table, the access request to the first memory and the second memory in parallel,
- detect hits with respect to the first memory, wherein each of the hits does not correspond to any valid page address in the prediction table, and
- prevent the prediction table from tracking the hits by a bypass of one or more of any entry allocation in the prediction table to the hits or any bit allocation in the prediction table to the hits.
7 more elements
(canceled)
A semiconductor package apparatus comprising:
- one or more substrates;
- and
- logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed functionality logic hardware, the logic coupled to the one or more substrates configured to:
- maintain a prediction table that tracks missed page addresses with respect to a first memory,
- send, if an access request does not correspond to any valid page address in the prediction table, the access request to the first memory,
- send, if the access request corresponds to a valid page address in the prediction table, the access request to the first memory and a second memory in parallel, wherein the first memory is associated with a shorter access time than the second memory,
- detect hits with respect to the first memory, wherein each of the hits does not correspond to any valid page address in the prediction table, and
- prevent the prediction table from tracking the hits by a bypass of one or more of any entry allocation in the prediction table to the hits or any bit allocation in the prediction table to the hits.
5 more elements
(canceled)
A method comprising:
- maintaining a prediction table that tracks missed page addresses with respect to a first memory;
- sending, if an access request does not correspond to any valid page address in the prediction table, the access request to the first memory;
- sending, if the access request corresponds to a valid page address in the prediction table, the access request to the first memory and a second memory in parallel, wherein the first memory is associated with a shorter access time than the second memory;
- detecting hits with respect to the first memory, wherein each of the hits does not correspond to any valid page address in the prediction table;
- and
- preventing the prediction table from tracking the hits by a bypass of one or more of any entry allocation in the prediction table to the hits or any bit allocation in the prediction table to the hits.
3 more elements
(canceled)
Dependencies are inferred from the claim text.